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author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-08 11:29:09 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-09 10:30:26 +0200 |
commit | 8c7241cf896f9aa5328ab50083f162bad1e6c248 (patch) | |
tree | dfd13d2468d104b1342da7ded269443d53b4a80e /Documentation/devicetree | |
parent | 3a7b7f26a68ee934e3537350e66119b3f6f7998d (diff) | |
download | barebox-8c7241cf896f9aa5328ab50083f162bad1e6c248.tar.gz barebox-8c7241cf896f9aa5328ab50083f162bad1e6c248.tar.xz |
DT: Add binding for Altera FPGAs in passive-serial mode
Altera FPGAs that are programmed via SPI use the passive serial protocol.
Add a simple binding that describes the setup for this usecase.
Cc: devicetree@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/firmware/altr,passive-serial.txt | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt b/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt new file mode 100644 index 0000000000..d357dd39cf --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt @@ -0,0 +1,24 @@ +Altera FPGAs in passive serial mode +----------------------------------- + +This binding defines the control interface to Altera FPGAs in +passive serial mode. This is used to upload the firmware and +to start the FPGA. + +Required properties: +- compatible: shall be "altr,fpga-passive-serial" +- reg: SPI chip select +- nstat-gpios: Specify GPIO for controlling the nstat pin +- confd-gpios: Specify GPIO for controlling the confd pin +- nconfig-gpios: Specify GPIO for controlling the nconfig pin + +Example: + + fpga@0 { + compatible = "altr,fpga-passive-serial"; + nstat-gpios = <&gpio4 18 0>; + confd-gpios = <&gpio4 19 0>; + nconfig-gpios = <&gpio4 20 0>; + spi-max-frequency = <10000000>; + reg = <0>; + }; |