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author | Juergen Borleis <jbe@pengutronix.de> | 2016-12-06 15:41:59 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-20 09:10:30 +0100 |
commit | eb101add591bfdf531e125df4e665047de108896 (patch) | |
tree | bc8c5f38bbb9df523f340883a451c926842c0948 /Documentation | |
parent | 99a464413e1552b0d0f6d4d504d35f66d6ef903d (diff) | |
download | barebox-eb101add591bfdf531e125df4e665047de108896.tar.gz barebox-eb101add591bfdf531e125df4e665047de108896.tar.xz |
ARM: i.MX: Add WaRP7 board support
Signed-off-by Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/boards/imx/Element14-WaRP7.rst | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/boards/imx/Element14-WaRP7.rst b/Documentation/boards/imx/Element14-WaRP7.rst new file mode 100644 index 0000000000..d4e5e79917 --- /dev/null +++ b/Documentation/boards/imx/Element14-WaRP7.rst @@ -0,0 +1,54 @@ +element14 WaRP7 +=============== + +This CPU card is based on an NXP i.MX7S SoC. + +Supported hardware +================== + +- NXP PMIC PFUZE3000 +- Kingston 08EMCP04-EL3AV100 eMCP (eMMC and LPDDR3 memory in one package) + - 8 GiB eMMC Triple-Level cell NAND flash, eMMC standard 5.0 (HS400) + - 512 MiB LPDDR3 SDRAM starting at address 0x80000000 + +Bootstrapping barebox +===================== + +The device boots in internal boot mode from eMMC and is shipped with a +vendor modified u-boot imximage. + +Barebox can be used as a drop-in replacement for the shipped bootloader. + +The WaRP7 IO Board has a double DIP switch where switch number two defines the +boot source of the i.MX7 SoC: + + +-----+ + | | + | | O | <--- on = high level + | | | | + | O | | <--- off = low level + | | + | 1 2 | + +-----+ + +Bootsource is the internal eMMC: + + +-----+ + | | + | O | | + | | | | + | | O | <---- eMMC + | | + | 1 2 | + +-----+ + +Bootsource is the USB: + + +-----+ + | | + | O O | <---- USB + | | | | + | | | | + | | + | 1 2 | + +-----+ |