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authorAhmad Fatoum <a.fatoum@pengutronix.de>2019-09-17 13:55:18 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-09-18 14:40:08 +0200
commit222e8d085efddb442c318824e5b027fd4e59594a (patch)
tree68ddd0099bc8e38377520575020e238ec4c70584 /Documentation
parentacc0e71a63c6cfc2fc849e20b2b5fcf8bb8fac3c (diff)
downloadbarebox-222e8d085efddb442c318824e5b027fd4e59594a.tar.gz
Documentation: boards: document layerscape support
Some peripherals are still missing, but the main functionality to boot an OS is already in place. Document how to use it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/boards/layerscape.rst61
-rw-r--r--Documentation/boards/layerscape/ls1046ardb.rst36
-rw-r--r--Documentation/boards/layerscape/tqmls1046a.rst49
3 files changed, 146 insertions, 0 deletions
diff --git a/Documentation/boards/layerscape.rst b/Documentation/boards/layerscape.rst
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+NXP Layerscape
+==============
+
+barebox has support for some of the ARM64 based Layerscape SoCs from NXP.
+
+Booting barebox
+---------------
+
+The Layerscape SoCs contain logic dubbed the Pre-Bootloader (PBL). This unit
+reads the boot medium and conducts basic IO multiplexing according to the RCW
+(Reset Configuration Word). The RCW then refers the PBL to the location of the
+Pre-Bootloader Instructions (PBI). These do basic device configuration and
+afterwards poke the barebox PBL into On-Chip SRAM.
+The barebox PBL then loads the complete barebox image and runs the PBL again,
+this time from SDRAM after it has been set up.
+
+For each board, a barebox image per supported boot medium is generated.
+They may differ in the RCW, PBI and endianess depending on the boot medium.
+
+Flashing barebox
+----------------
+
+The barebox binary is expected to be located 4K bytes into the SD-Card::
+
+ dd if=images/barebox-${boardname}-sd.image of=/dev/sdX bs=512 seek=8
+
+From there on, ``barebox_update`` can be used to flash
+barebox to the QSPI NOR-Flash if required::
+
+ barebox_update -t qspi /mnt/tftp/barebox-${global.hostname}-qspi.imaag
+
+Flashing to the eMMC is possible likewise::
+
+ barebox_update -t sd /mnt/tftp/barebox-${global.hostname}-sd.imaag
+
+.. note:: Some SoCs like the LS1046A feature only a single eSDHC.
+ In such a case, using eMMC and SD-Card at the same time is not possible.
+ Boot from QSPI to flash the eMMC.
+
+Firmware Blobs
+--------------
+
+Network: `fsl_fman_ucode_ls1046_r1.0_106_4_18.bin <https://github.com/NXP/qoriq-fm-ucode/raw/integration/fsl_fman_ucode_ls1046_r1.0_106_4_18.bin>`_.
+
+PSCI Firmware: `ppa-ls1046a.bin <https://github.com/NXP/qoriq-ppa-binary/raw/integration/soc-ls1046/ppa.itb>`_.
+
+Layerscape boards
+-----------------
+
+With multi-image and device trees, it's expected to have ``layerscape_defconfig``
+as sole defconfig for all Layerscape boards::
+
+ make ARCH=arm layerscape_defconfig
+
+Generated images will be placed under ``images/``.
+
+.. toctree::
+ :glob:
+ :maxdepth: 1
+
+ layerscape/*
diff --git a/Documentation/boards/layerscape/ls1046ardb.rst b/Documentation/boards/layerscape/ls1046ardb.rst
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+NXP LS1046A Reference Design Board
+==================================
+
+Boot DIP Switches
+-----------------
+
+Boot source selection happens via the the bottom most DIP switch (near the micro-usb port)::
+
+ OFF -> ON
+ +---------+
+ 1 | O---- |
+ 2 | O---- |
+ 3 | ----O |
+ 4 | O---- |
+ 5 | O---- |
+ 6 | O---- |
+ 7 | ----O | <---- Boot from QSPI (default)
+ 8 | O---- |
+ +---------+
+
+ OFF -> ON
+ +---------+
+ 1 | O---- |
+ 2 | O---- |
+ 3 | ----O |
+ 4 | O---- |
+ 5 | O---- |
+ 6 | O---- |
+ 7 | O---- | <---- Boot from SDHC
+ 8 | O---- |
+ +---------+
+
+Known Issues
+------------
+
+System reset may not complete if the CMSIS-DAP micro-usb is connected.
diff --git a/Documentation/boards/layerscape/tqmls1046a.rst b/Documentation/boards/layerscape/tqmls1046a.rst
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+TQ-Group TQMLS1046A Module
+==========================
+
+Ethernet Ports
+--------------
+
+There two RGMII ports are the two closest to the RS-232 socket.
+They are ``eth2`` for the lower port and ``eth3`` for the upper port.
+
+MBLS10xxA (Base Board) Boot DIP Switches
+----------------------------------------
+
+Boot source selection happens via the ``S5`` DIP-Switch::
+
+ +---------+
+ | |
+ | | | O x |
+ | | | | x | <---- SDHC (X31)
+ | O O | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+ +---------+
+ | |
+ | O | O x |
+ | | | | x | <---- eMMC
+ | | O | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+ +---------+
+ | |
+ | | O O x |
+ | | | | x | <---- QSPI (eSDHC controls SDHC)
+ | O | | x |
+ | |
+ | 1 2 3 4 |
+ +---------+
+
+ +---------+
+ | |
+ | O O O x |
+ | | | | x | <---- QSPI (eSDHC controls eMMC)
+ | | | | x |
+ | |
+ | 1 2 3 4 |
+ +---------+