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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-10-01 12:09:49 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-10-05 09:05:37 +0200 |
| commit | 35d4cf996034badd45b80c9fcd61e53036786421 (patch) | |
| tree | 71b9cb0a3b2b9b893bd1aec03f8f752bf24e798f /Documentation | |
| parent | c4d8f7744687100abcc0b45e7e2ff1af2b681537 (diff) | |
| download | barebox-35d4cf996034badd45b80c9fcd61e53036786421.tar.gz barebox-35d4cf996034badd45b80c9fcd61e53036786421.tar.xz | |
ARM: i.MX8MN: add i.MX8MN-EVK support
With driver support in place, we can now build and run barebox in the
i.MX8MN. Following tested working:
- Setting up DDR4 SDRAM
- Booting from SD-Card
- Booting from eMMC
- Updating barebox in SD-Card/eMMC boot partition
- USB Fastboot, ACM gadgets
- UART
- Early I2C with bd71837
- Ethernet
- Loading and communicating with TF-A
The resulting image supports both DDR4 and LPDDR4. They use different
PMICs, so probing the i2c addresses of them indicates what DRAM type
to setup. I have only tested this on a DDR4 EVK, but the LPDDR4 code
is equivalent to what's already used in barebox with i.MX8M Mini
and Plus, so it should work(tm).
Notably missing:
- boot from USB SDP doesn't work. early debug_ll doesn't indicate
that barebox PBL was actually entered.
This can follow later though.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20211001100949.6891-9-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/boards/imx/nxp-imx8mn-evk.rst | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/Documentation/boards/imx/nxp-imx8mn-evk.rst b/Documentation/boards/imx/nxp-imx8mn-evk.rst new file mode 100644 index 0000000000..44cd0c68e4 --- /dev/null +++ b/Documentation/boards/imx/nxp-imx8mn-evk.rst @@ -0,0 +1,60 @@ +NXP i.MX8MN EVK Evaluation Board +================================ + +Board comes with either: + +* 2GiB of LPDDR4 RAM +* 2GiB of DDR4 RAM + +barebox supports both variants with the same image. + +Downloading DDR PHY Firmware +---------------------------- + +As a part of DDR intialization routine NXP i.MX8MN EVK requires and +uses several binary firmware blobs that are distributed under a +separate EULA and cannot be included in Barebox. In order to obtain +them do the following:: + + wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.12.bin + chmod +x firmware-imx-8.12.bin + ./firmware-imx-8.12.bin + +Executing that file should produce a EULA acceptance dialog as well as +result in the following files: + +- lpddr4_pmu_train_1d_dmem.bin +- lpddr4_pmu_train_1d_imem.bin +- lpddr4_pmu_train_2d_dmem.bin +- lpddr4_pmu_train_2d_imem.bin +- ddr4_dmem_1d_201810.bin +- ddr4_imem_1d_201810.bin +- ddr4_dmem_2d_201810.bin +- ddr4_imem_2d_201810.bin + +As a last step of this process those files need to be placed in +"firmware/":: + + for f in lpddr4_pmu_train_1d_dmem.bin \ + lpddr4_pmu_train_1d_imem.bin \ + lpddr4_pmu_train_2d_dmem.bin \ + lpddr4_pmu_train_2d_imem.bin; \ + do \ + cp firmware-imx-8.0/firmware/ddr/synopsys/${f} \ + firmware/${f}; \ + done + + for f in ddr4_dmem_1d_201810.bin \ + ddr4_imem_1d_201810.bin \ + ddr4_dmem_2d_201810.bin \ + ddr4_imem_2d_201810.bin; \ + do \ + cp firmware-imx-8.0/firmware/ddr/synopsys/${f} \ + firmware/${f%_201810.bin}.bin; \ + done + +Build barebox +============= + + make imx_v8_defconfig + make |