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authorAntony Pavlov <antonynpavlov@gmail.com>2021-06-14 17:27:53 +0300
committerSascha Hauer <s.hauer@pengutronix.de>2021-06-15 11:16:25 +0200
commitfd04aa73d8945b55ca604b490fc3f6c58bb7771b (patch)
tree7dfddb14a00e4dbdcb75e2b57ec46e4d5d49aa7c /Documentation
parent7689055a8b037363dae840eee33a0ed43f905b7a (diff)
downloadbarebox-fd04aa73d8945b55ca604b490fc3f6c58bb7771b.tar.gz
barebox-fd04aa73d8945b55ca604b490fc3f6c58bb7771b.tar.xz
Documentation: RISC-V: erizo: fix header level
The "Running on DE0-Nano FPGA board" is a "Erizo" subsection not independent section. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20210614142753.86477-1-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/boards/riscv.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
index 59cdc00a99..387b86c588 100644
--- a/Documentation/boards/riscv.rst
+++ b/Documentation/boards/riscv.rst
@@ -122,7 +122,7 @@ Run barebox::
Running on DE0-Nano FPGA board
-------------------------------
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
See https://github.com/open-design/riscv-soc-cores/ for instructions
on DE0-Nano bitstream generation and loading.