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authorBen Warren <bwarren@qstreams.com>2006-09-07 16:50:54 -0400
committerKim Phillips <kim.phillips@freescale.com>2006-11-03 19:42:19 -0600
commitbb99ad6d8257bf828f150d40f507b30d80a4a7ae (patch)
treeb097750e9e63f49186717a1eb4fcd078f65ae381 /README
parentbed85caf872714ebf53013967a695c9d63acfc68 (diff)
downloadbarebox-bb99ad6d8257bf828f150d40f507b30d80a4a7ae.tar.gz
barebox-bb99ad6d8257bf828f150d40f507b30d80a4a7ae.tar.xz
Add support for multiple I2C buses
Hello, Attached is a patch providing support for multiple I2C buses at the command level. The second part of the patch includes an implementation for the MPC834x CPU and MPC8349EMDS board. /*** Note: This patch replaces ticket DNX#2006083042000018 ***/ Signed-off-by: Ben Warren <bwarren@qstreams.com> Overview: 1. Include new 'i2c' command (based on USB implementation) using CONFIG_I2C_CMD_TREE. 2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that the commands to change bus number and speed are only available under the new 'i2c' command mentioned in the first bullet. 3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form of an array of bus-device pairs. Otherwise, it is an array of uchar. CHANGELOG: Added new 'i2c' master command for all I2C interaction. This is conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for setting I2C bus speed as well as changing the active bus if the board has more than one (conditionally compiled with CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses. Updated README. regards, Ben
Diffstat (limited to 'README')
-rw-r--r--README42
1 files changed, 41 insertions, 1 deletions
diff --git a/README b/README
index b78ea6124d..6b94f8482c 100644
--- a/README
+++ b/README
@@ -1207,7 +1207,12 @@ The following options need to be configured:
clock chips. See common/cmd_i2c.c for a description of the
command line interface.
- CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
+ CONFIG_I2C_CMD_TREE is a recommended option that places
+ all I2C commands under a single 'i2c' root command. The
+ older 'imm', 'imd', 'iprobe' etc. commands are considered
+ deprecated and may disappear in the future.
+
+ CONFIG_HARD_I2C selects a hardware I2C controller.
CONFIG_SOFT_I2C configures u-boot to use a software (aka
bit-banging) driver instead of CPM or similar hardware
@@ -1312,6 +1317,31 @@ The following options need to be configured:
in u-boot bd_info structure based on u-boot environment
variable "i2cfast". (see also i2cfast)
+ CONFIG_I2C_MULTI_BUS
+
+ This option allows the use of multiple I2C buses, each of which
+ must have a controller. At any point in time, only one bus is
+ active. To switch to a different bus, use the 'i2c dev' command.
+ Note that bus numbering is zero-based.
+
+ CFG_I2C_NOPROBES
+
+ This option specifies a list of I2C devices that will be skipped
+ when the 'i2c probe' command is issued (or 'iprobe' using the legacy
+ command). If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device
+ pairs. Otherwise, specify a 1D array of device addresses
+
+ e.g.
+ #undef CONFIG_I2C_MULTI_BUS
+ #define CFG_I2C_NOPROBES {0x50,0x68}
+
+ will skip addresses 0x50 and 0x68 on a board with one I2C bus
+
+ #define CONFIG_I2C_MULTI_BUS
+ #define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
+
+ will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
+
- SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
@@ -2209,6 +2239,16 @@ Low Level (hardware related) configuration options:
CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+- CONFIG_SPD_EEPROM
+ Get DDR timing information from an I2C EEPROM. Common with pluggable
+ memory modules such as SODIMMs
+ SPD_EEPROM_ADDRESS
+ I2C address of the SPD EEPROM
+
+- CFG_SPD_BUS_NUM
+ If SPD EEPROM is on an I2C bus other than the first one, specify here.
+ Note that the value must resolve to something your driver can deal with.
+
- CONFIG_ETHER_ON_FEC[12]
Define to enable FEC[12] on a 8xx series processor.