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| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2017-04-28 16:41:41 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-05-03 13:51:22 +0200 |
| commit | d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa (patch) | |
| tree | a3dbd48b1feef91687bd75e9227870debbbbf9cb /arch/arm/Kconfig | |
| parent | db3feb61d19060a0589f3906a8a081bebd934ace (diff) | |
| download | barebox-d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa.tar.gz barebox-d5c8bc3ff1a795cb9ef44abd518f5dae6f9000fa.tar.xz | |
ARM: socfpga: add arria10 support
Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that
is already supported in barebox.
Both a the same in some parts, but totaly different in
others. Most of the hardware blocks are the same in the
SoC parts. The OCRAM is larger on the Arria10 and the
SDRAM controller is different.
The serial core only supports 32bit accesses (different to
the 8bit accesses on the Cyclone5).
As Arria10 has 256KB of OCRAM, it is possible to fit a larger
barebox (and/or use PBL) instead of the two stage bootprocess
used on the Cyclone5 and its 64KB OCRAM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2583e9dd1b..e7edc2ad44 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -169,7 +169,7 @@ config ARCH_ROCKCHIP select ARCH_HAS_L2X0 config ARCH_SOCFPGA - bool "Altera SOCFPGA cyclone5" + bool "Altera SOCFPGA" select HAS_DEBUG_LL select ARM_SMP_TWD select CPU_V7 @@ -177,8 +177,8 @@ config ARCH_SOCFPGA select CLKDEV_LOOKUP select GPIOLIB select HAVE_PBL_MULTI_IMAGES - select OFDEVICE if !ARCH_SOCFPGA_XLOAD - select OFTREE if !ARCH_SOCFPGA_XLOAD + select OFDEVICE if !(ARCH_SOCFPGA_XLOAD && ARCH_SOCFPGA_CYCLONE5) + select OFTREE if !(ARCH_SOCFPGA_XLOAD && ARCH_SOCFPGA_CYCLONE5) config ARCH_S3C24xx bool "Samsung S3C2410, S3C2440" |