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authorJuergen Beisert <jbe@pengutronix.de>2012-01-02 12:44:01 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2012-01-02 13:32:14 +0100
commit59994faae6162e0e29a0add7cd24023eac0c9580 (patch)
treee1ad4ae7e4b0f66dd3f6ac0c0e7d2b2ec59cf4a0 /arch/arm/boards/a9m2440/lowlevel_init.S
parentb8560b2b2f9a12baf42ca6cf426bd59342d4e0a3 (diff)
downloadbarebox-59994faae6162e0e29a0add7cd24023eac0c9580.tar.gz
barebox-59994faae6162e0e29a0add7cd24023eac0c9580.tar.xz
MACH SAMSUNG/S3C: Re-work the memory detection and handling
Keep common code in the MACH instead of re-inventing it in each platform. Also use S3C* macros for all memory related register. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/a9m2440/lowlevel_init.S')
-rw-r--r--arch/arm/boards/a9m2440/lowlevel_init.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index bfdd7f0630..57ebe3fbfc 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -37,7 +37,7 @@ sdram_init:
ldr r4, [r1]
and r4, r4, #0x3
- ldr r1, =S3C24X0_MEMCTL_BASE
+ ldr r1, =S3C_MEMCTL_BASE
/* configure both SDRAM areas with 32 bit data bus width */
ldr r0, =((0x2 << 24) + (0x2 << 28))
str r0, [r1], #0x1c /* post add register offset for bank6 */
@@ -218,9 +218,9 @@ board_init_lowlevel:
bl s3c24x0_disable_wd
/* skip everything here if we are already running from SDRAM */
- cmp pc, #S3C24X0_SDRAM_BASE
+ cmp pc, #S3C_SDRAM_BASE
blo 1f
- cmp pc, #S3C24X0_SDRAM_END
+ cmp pc, #S3C_SDRAM_END
bhs 1f
mov pc, r10