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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-16 14:01:09 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-16 14:01:09 +0100 |
| commit | bf38ac7b89dee71d14d4d65e9ad0d0cb727cbb98 (patch) | |
| tree | 3cf8336e5c2c6341120a2b68f8bb7a5df385fb64 /arch/arm/boards/eukrea_cpuimx25/lowlevel.c | |
| parent | 38c75d0f112d4e8bc3762cd8d0b6dbae3cf7e441 (diff) | |
| parent | 4f2ac27e2503e15bffdebca4757e02638686fe94 (diff) | |
| download | barebox-bf38ac7b89dee71d14d4d65e9ad0d0cb727cbb98.tar.gz barebox-bf38ac7b89dee71d14d4d65e9ad0d0cb727cbb98.tar.xz | |
Merge branch 'for-next/imx'
Conflicts:
arch/arm/boards/guf-neso/lowlevel.c
arch/arm/boards/pcm038/lowlevel.c
commands/Makefile
Diffstat (limited to 'arch/arm/boards/eukrea_cpuimx25/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx25/lowlevel.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 8d6cd1f982..36ce98bc69 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -19,7 +19,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <io.h> @@ -56,15 +56,15 @@ void __bare_init __naked reset(void) common_reset(); /* restart the MPLL and wait until it's stable */ - writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27), - MX25_CCM_BASE_ADDR + CCM_CCTL); - while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {}; + writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27), + MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); + while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {}; /* Configure dividers and ARM clock source * ARM @ 400 MHz * AHB @ 133 MHz */ - writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); /* Enable UART1 / FEC / */ /* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0); @@ -117,10 +117,10 @@ void __bare_init __naked reset(void) writel(0x1, 0xb8003000); /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2); + r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); r &= ~0xf; r |= 0x1; - writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2); + writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -128,22 +128,22 @@ void __bare_init __naked reset(void) board_init_lowlevel_return(); /* Init Mobile DDR */ - writel(0x0000000E, ESDMISC); - writel(0x00000004, ESDMISC); + writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops)); - writel(0x0029572B, ESDCFG0); - writel(0x92210000, ESDCTL0); + writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400); - writel(0xA2210000, ESDCTL0); + writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR); writeb(0xda, MX25_CSD0_BASE_ADDR); - writel(0xB2210000, ESDCTL0); + writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); - writel(0x82216080, ESDCTL0); + writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ |