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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-10 22:10:36 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-17 20:22:02 +0200 |
| commit | 6a9d37e579b7922b427d02aa02a9f104b378a628 (patch) | |
| tree | a95ce6c274170c673de122c90de392c8c3cb917f /arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | |
| parent | 11b175793714f7461e91bc00120c7f6e8b2fdc5a (diff) | |
| download | barebox-6a9d37e579b7922b427d02aa02a9f104b378a628.tar.gz barebox-6a9d37e579b7922b427d02aa02a9f104b378a628.tar.xz | |
ARM i.MX27: Cleanup remaining unprefixed registers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S')
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index eac9ecc2e2..bab5c8c211 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -25,11 +25,12 @@ /* Enable DDR SDRAM operation */ writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(0x55555555, DSCR(3)) /* Set the driving strength */ - writel(0x55555555, DSCR(5)) - writel(0x55555555, DSCR(6)) - writel(0x00005005, DSCR(7)) - writel(0x15555555, DSCR(8)) + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) /* Initial reset */ writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) @@ -75,23 +76,26 @@ reset: common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* disable mpll/spll */ - ldr r0, =CSCR + ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR ldr r1, [r0] bic r1, r1, #0x03 str r1, [r0] - + /* * pll clock initialization - see section 3.4.3 of the i.MX27 manual */ - writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */ - writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */ - writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + /* MPLL = 399 MHz */ + writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 240 MHz */ + writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) + writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) /* add some delay here */ mov r1, #0x1000 @@ -99,12 +103,14 @@ reset: bne 1b /* clock gating enable */ - writel(0x00050f08, GPCR) + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) /* peripheral clock divider */ - writel(0x130400c3, PCDR0) /* FIXME */ - writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz */ + /* FIXME */ + writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0) + /* PERDIV1=08 @133 MHz */ + writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1) + /* PERDIV1=04 @266 MHz */ /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 |