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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-09 21:11:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-17 20:22:01 +0200 |
| commit | 7a334ccdece70ed769af6c1604e488b942685a03 (patch) | |
| tree | a4351432ecba41fc67dc967349b80aaf6e2d81a9 /arch/arm/boards/eukrea_cpuimx35 | |
| parent | aaad5cbad757b21457874a6b7adbeaaad36a0ce3 (diff) | |
| download | barebox-7a334ccdece70ed769af6c1604e488b942685a03.tar.gz barebox-7a334ccdece70ed769af6c1604e488b942685a03.tar.xz | |
ARM i.MX: Use SoC specific base to access sdram controller registers
This redefines the sdram controller registers as offsets to the base
rather than as absolute addresses. All users are fixed to use the
SoC specific base address.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/eukrea_cpuimx35')
| -rw-r--r-- | arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index ea932f773e..7f9395e291 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -138,22 +138,22 @@ void __bare_init __naked reset(void) board_init_lowlevel_return(); /* Init Mobile DDR */ - writel(0x0000000E, ESDMISC); - writel(0x00000004, ESDMISC); + writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops)); - writel(0x0009572B, ESDCFG0); - writel(0x92220000, ESDCTL0); + writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); - writel(0xA2220000, ESDCTL0); + writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR); writeb(0xda, MX35_CSD0_BASE_ADDR); - writel(0xB2220000, ESDCTL0); + writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); - writel(0x82228080, ESDCTL0); + writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ |