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author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-09-22 15:13:57 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-04 15:19:52 +0200 |
commit | 862a8680693130e0237c89bf20a3d16ac38a2c0a (patch) | |
tree | dfd5724b5c491dc42160d819758021713f527b16 /arch/arm/boards/eukrea_cpuimx35 | |
parent | ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 (diff) | |
download | barebox-862a8680693130e0237c89bf20a3d16ac38a2c0a.tar.gz barebox-862a8680693130e0237c89bf20a3d16ac38a2c0a.tar.xz |
ARM i.MX35: give register base addresses a proper MX35_ prefix
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/eukrea_cpuimx35')
-rw-r--r-- | arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c | 100 | ||||
-rw-r--r-- | arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 24 |
2 files changed, 62 insertions, 62 deletions
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 3c7fb6992e..53cc428c84 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -97,21 +97,21 @@ static void imx35_usb_init(void) unsigned int tmp; /* Host 1 */ - tmp = readl(IMX_OTG_BASE + 0x600); + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x600); tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; tmp |= MX35_H1_USBTE_BIT | MX35_H1_PM_BIT | MX35_H1_TLL_BIT ; tmp |= MX35_H1_IPPUE_DOWN_BIT; - writel(tmp, IMX_OTG_BASE + 0x600); + writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x600); - tmp = readl(IMX_OTG_BASE + 0x584); + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x584); tmp |= 3 << 30; - writel(tmp, IMX_OTG_BASE + 0x584); + writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x584); /* Set to Host mode */ - tmp = readl(IMX_OTG_BASE + 0x5a8); - writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x5a8); + writel(tmp | 0x3, MX35_USB_OTG_BASE_ADDR + 0x5a8); } #endif @@ -124,7 +124,7 @@ static struct fsl_usb2_platform_data usb_pdata = { static int eukrea_cpuimx35_mem_init(void) { - arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024); + arm_add_mem_device("ram0", MX35_CSD0_BASE_ADDR, 128 * 1024 * 1024); return 0; } @@ -216,13 +216,13 @@ static int eukrea_cpuimx35_devices_init(void) #ifdef CONFIG_USB imx35_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX35_USB_HS_BASE_ADDR, NULL); #endif #ifdef CONFIG_USB_GADGET /* Workaround ENGcm09152 */ - tmp = readl(IMX_OTG_BASE + 0x608); - writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608); - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200, + tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608); + writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608); + add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200, IORESOURCE_MEM, &usb_pdata); #endif armlinux_set_bootparams((void *)0x80000100); @@ -246,70 +246,70 @@ static int eukrea_cpuimx35_core_init(void) u32 reg; /* enable clock for I2C1, SDHC1, USB and FEC */ - reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); reg |= 0x3 << CCM_CGR1_FEC_SHIFT; reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT; reg |= 0x3 << CCM_CGR1_I2C1_SHIFT, - reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); - reg = readl(IMX_CCM_BASE + CCM_CGR2); + reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2); reg |= 0x3 << CCM_CGR2_USB_SHIFT; - reg = writel(reg, IMX_CCM_BASE + CCM_CGR2); + reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, IMX_AIPS1_BASE); - writel(0x77777777, IMX_AIPS1_BASE + 0x4); - writel(0x77777777, IMX_AIPS2_BASE); - writel(0x77777777, IMX_AIPS2_BASE + 0x4); + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ - writel(0x0, IMX_AIPS1_BASE + 0x40); - writel(0x0, IMX_AIPS1_BASE + 0x44); - writel(0x0, IMX_AIPS1_BASE + 0x48); - writel(0x0, IMX_AIPS1_BASE + 0x4C); - reg = readl(IMX_AIPS1_BASE + 0x50); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); reg &= 0x00FFFFFF; - writel(reg, IMX_AIPS1_BASE + 0x50); + writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); - writel(0x0, IMX_AIPS2_BASE + 0x40); - writel(0x0, IMX_AIPS2_BASE + 0x44); - writel(0x0, IMX_AIPS2_BASE + 0x48); - writel(0x0, IMX_AIPS2_BASE + 0x4C); - reg = readl(IMX_AIPS2_BASE + 0x50); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); reg &= 0x00FFFFFF; - writel(reg, IMX_AIPS2_BASE + 0x50); + writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); /* MAX (Multi-Layer AHB Crossbar Switch) setup */ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ #define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ - writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ /* SGPCR - always park on last master */ - writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ - writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ - writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ - writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ - writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ /* MGPCR - restore default values */ - writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ - writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ - writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ - writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ - writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ - writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ /* * M3IF Control Register (M3IFCTL) @@ -324,7 +324,7 @@ static int eukrea_cpuimx35_core_init(void) * ------------ * 0x00000040 */ - writel(0x40, IMX_M3IF_BASE); + writel(0x40, MX35_M3IF_BASE_ADDR); return 0; } @@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index 2721cf2ff0..ea932f773e 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -41,10 +41,10 @@ static void __bare_init __naked insdram(void) uint32_t r; /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(IMX_CCM_BASE + CCM_PDR4); + r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); r &= ~(0xf << 28); r |= 0x1 << 28; - writel(r, IMX_CCM_BASE + CCM_PDR4); + writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ r = STACK_BASE + STACK_SIZE - 12; @@ -59,7 +59,7 @@ static void __bare_init __naked insdram(void) void __bare_init __naked reset(void) { uint32_t r, s; - unsigned long ccm_base = IMX_CCM_BASE; + unsigned long ccm_base = MX35_CCM_BASE_ADDR; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; int i; @@ -128,9 +128,9 @@ void __bare_init __naked reset(void) r |= 0x03000000; writel(r, ccm_base + CCM_CGR2); - r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL); + r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; - writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL); + writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -146,22 +146,22 @@ void __bare_init __naked reset(void) writel(0x0009572B, ESDCFG0); writel(0x92220000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0 + 0x400); + writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); writel(0xA2220000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0); - writeb(0xda, IMX_SDRAM_CS0); + writeb(0xda, MX35_CSD0_BASE_ADDR); + writeb(0xda, MX35_CSD0_BASE_ADDR); writel(0xB2220000, ESDCTL0); - writeb(0xda, IMX_SDRAM_CS0 + 0x33); - writeb(0xda, IMX_SDRAM_CS0 + 0x2000000); + writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); + writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); writel(0x82228080, ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ r = get_pc(); - if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + if (r < MX35_NFC_BASE_ADDR || r > MX35_NFC_BASE_ADDR + 0x800) board_init_lowlevel_return(); - src = (unsigned int *)IMX_NFC_BASE; + src = (unsigned int *)MX35_NFC_BASE_ADDR; trg = (unsigned int *)_text; /* Move ourselves out of NFC SRAM */ |