ARM: rename boards to more consistent naming

This renames the Freescale and Phytec board directories and defconfig
files to a common naming scheme. The board directories are named
<vendor>-<board> and the defconfig files are named
<vendor>-<board>_defconfig. Also the DataModul realq7 is renamed to its
Marketing Name eDM-QMX6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

7 files changed, 928 insertions, 0 deletions

diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.c b/arch/arm/boards/freescale-mx35-3ds/3stack.c
new file mode 100644
index 0000000000..dbd1c7adcb
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/3stack.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ *               2009 Marc Kleine-Budde, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Derived from:
+ *
+ * * mx35_3stack.c - board file for uboot-v1
+ *   Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *   (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <fec.h>
+#include <fs.h>
+#include <init.h>
+#include <nand.h>
+#include <net.h>
+#include <sizes.h>
+#include <partition.h>
+#include <gpio.h>
+
+#include <asm/armlinux.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <io.h>
+#include <generated/mach-types.h>
+
+#include <mach/weim.h>
+#include <mach/imx-nand.h>
+#include <mach/imx35-regs.h>
+#include <mach/iomux-mx35.h>
+#include <mach/iomux-v3.h>
+#include <mach/imx-ipu-fb.h>
+#include <mach/generic.h>
+#include <mach/devices-imx35.h>
+#include <mach/revision.h>
+
+#include <i2c/i2c.h>
+#include <mfd/mc13xxx.h>
+#include <mfd/mc9sdz60.h>
+
+
+/* Board rev for the PDK 3stack */
+#define MX35PDK_BOARD_REV_1		0
+#define MX35PDK_BOARD_REV_2		1
+
+static struct fec_platform_data fec_info = {
+	.xcv_type	= PHY_INTERFACE_MODE_MII,
+	.phy_addr	= 0x1F,
+};
+
+struct imx_nand_platform_data nand_info = {
+	.hw_ecc		= 1,
+	.flash_bbt	= 1,
+};
+
+static struct i2c_board_info i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("mc13892", 0x08),
+	}, {
+		I2C_BOARD_INFO("mc9sdz60", 0x69),
+	},
+};
+
+/*
+ * Generic display, shipped with the PDK
+ */
+static struct fb_videomode CTP_CLAA070LC0ACW = {
+	/* 800x480 @ 60 Hz */
+	.name		= "CTP-CLAA070LC0ACW",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= KHZ2PICOS(27000),
+	.left_margin	= 50,
+	.right_margin	= 50,	/* whole line should have 900 clocks */
+	.upper_margin	= 10,
+	.lower_margin	= 10,	/* whole frame should have 500 lines */
+	.hsync_len	= 1,	/* note: DE only display */
+	.vsync_len	= 1,	/* note: DE only display */
+	.sync		= FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+	.vmode		= FB_VMODE_NONINTERLACED,
+	.flag		= 0,
+};
+
+static struct imx_ipu_fb_platform_data ipu_fb_data = {
+	.mode		= &CTP_CLAA070LC0ACW,
+	.num_modes	= 1,
+	.bpp		= 16,
+};
+
+/*
+ * Revision to be passed to kernel. The kernel provided
+ * by freescale relies on this.
+ *
+ * C --> CPU type
+ * S --> Silicon revision
+ * B --> Board rev
+ *
+ * 31    20     16     12    8      4     0
+ *        | Cmaj | Cmin | B  | Smaj | Smin|
+ *
+ * e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2
+*/
+static unsigned int imx35_3ds_system_rev = 0x00035000;
+
+static void set_silicon_rev( int rev)
+{
+	imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF);
+}
+
+static void set_board_rev(int rev)
+{
+	imx35_3ds_system_rev =  (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+static int f3s_devices_init(void)
+{
+	uint32_t reg;
+
+	/* CS0: Nor Flash */
+	imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
+
+	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
+	/* some fuses provide us vital information about connected hardware */
+	if (reg & 0x20000000)
+		nand_info.width = 2;	/* 16 bit */
+	else
+		nand_info.width = 1;	/* 8 bit */
+
+	/*
+	 * This platform supports NOR and NAND
+	 */
+	imx35_add_nand(&nand_info);
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
+
+	switch ((reg >> 25) & 0x3) {
+	case 0x01:		/* NAND is the source */
+		devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
+		dev_add_bb_dev("self_raw", "self0");
+		devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
+		dev_add_bb_dev("env_raw", "env0");
+		break;
+
+	case 0x00:		/* NOR is the source */
+		devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+		devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
+		protect_file("/dev/env0", 1);
+		break;
+	}
+
+	set_silicon_rev(imx_silicon_revision());
+
+	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+	imx35_add_i2c0(NULL);
+
+	imx35_add_fec(&fec_info);
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL,	MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
+			IORESOURCE_MEM, NULL);
+
+	imx35_add_mmc0(NULL);
+
+	imx35_add_fb(&ipu_fb_data);
+
+	armlinux_set_architecture(MACH_TYPE_MX35_3DS);
+
+	return 0;
+}
+
+device_initcall(f3s_devices_init);
+
+static int f3s_enable_display(void)
+{
+	/* Enable power to the LCD. (bit 6 hi.) */
+	mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40);
+
+	return 0;
+}
+
+late_initcall(f3s_enable_display);
+
+static iomux_v3_cfg_t f3s_pads[] = {
+	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+	MX35_PAD_FEC_COL__FEC_COL,
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX35_PAD_FEC_MDC__FEC_MDC,
+	MX35_PAD_FEC_MDIO__FEC_MDIO,
+	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+	MX35_PAD_FEC_CRS__FEC_CRS,
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+
+	MX35_PAD_RXD1__UART1_RXD_MUX,
+	MX35_PAD_TXD1__UART1_TXD_MUX,
+	MX35_PAD_RTS1__UART1_RTS,
+	MX35_PAD_CTS1__UART1_CTS,
+
+	MX35_PAD_I2C1_CLK__I2C1_SCL,
+	MX35_PAD_I2C1_DAT__I2C1_SDA,
+
+	MX35_PAD_WDOG_RST__GPIO1_6,
+	MX35_PAD_COMPARE__GPIO1_5,
+
+	/* Display */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
+};
+
+static int f3s_console_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
+
+	barebox_set_model("Freescale i.MX35 3DS");
+	barebox_set_hostname("mx35-3stack");
+
+	imx35_add_uart0();
+	return 0;
+}
+
+console_initcall(f3s_console_init);
+
+static int f3s_core_init(void)
+{
+	u32 reg;
+
+	/* CS5: smc9117 */
+	imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00);
+
+	/* enable clock for I2C1 and FEC */
+	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+	reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
+	reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
+	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
+
+	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
+	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
+	reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
+	reg &= 0x00FFFFFF;
+	writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
+
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
+	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
+	reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
+	reg &= 0x00FFFFFF;
+	writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
+
+	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_PARAM1 0x00302154
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
+	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
+
+	/* SGPCR - always park on last master */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
+	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
+
+	/* MGPCR - restore default values */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
+	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
+
+	return 0;
+}
+
+core_initcall(f3s_core_init);
+
+static int f3s_get_rev(struct mc13xxx *mc13xxx)
+{
+	u32 rev;
+	int err;
+
+	err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev);
+	if (err)
+		return err;
+
+	if (rev == 0x00ffffff)
+		return -ENODEV;
+
+	return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1;
+}
+
+static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx)
+{
+	int err = 0;
+
+	/* COMPARE pin (GPIO1_5) as output and set high */
+	gpio_direction_output( 32*0 + 5 , 1);
+
+	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03);
+	err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01);
+	if (err)
+		printf("mc13892 Init sequence failed, the system might not be working!\n");
+
+	return err;
+}
+
+static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
+{
+	int err = 0;
+
+	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04);
+
+	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00);
+	mdelay(200);
+	err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80);
+
+	if (err)
+		dev_err(&mc9sdz60->client->dev,
+			"Init sequence failed, the system might not be working!\n");
+
+	return err;
+}
+
+static int f3s_pmic_init(void)
+{
+	struct mc13xxx *mc13xxx;
+	struct mc9sdz60 *mc9sdz60;
+	int rev;
+
+	mc13xxx = mc13xxx_get();
+	if (!mc13xxx) {
+		printf("FAILED to get PMIC handle!\n");
+		return 0;
+	}
+
+	rev = f3s_get_rev(mc13xxx);
+	switch (rev) {
+	case MX35PDK_BOARD_REV_1:
+		break;
+	case MX35PDK_BOARD_REV_2:
+		f3s_pmic_init_v2(mc13xxx);
+		break;
+	default:
+		printf("FAILED to identify board revision!\n");
+		return 0;
+	}
+
+	set_board_rev(rev);
+	printf("i.MX35 PDK CPU board version %d.\n", rev );
+
+	mc9sdz60 = mc9sdz60_get();
+	if (!mc9sdz60) {
+		printf("FAILED to get mc9sdz60 handle!\n");
+		return 0;
+	}
+
+	f3s_pmic_init_all(mc9sdz60);
+
+	armlinux_set_revision(imx35_3ds_system_rev);
+
+	return 0;
+}
+
+late_initcall(f3s_pmic_init);
diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.dox b/arch/arm/boards/freescale-mx35-3ds/3stack.dox
new file mode 100644
index 0000000000..15c5b6e1ff
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/3stack.dox
@@ -0,0 +1,4 @@
+/** @page the3stack Freescale MX35 3-Stack Board
+
+
+*/
diff --git a/arch/arm/boards/freescale-mx35-3ds/Makefile b/arch/arm/boards/freescale-mx35-3ds/Makefile
new file mode 100644
index 0000000000..a1110c2e0b
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/Makefile
@@ -0,0 +1,4 @@
+
+obj-y					+= 3stack.o
+lwl-y					+= lowlevel_init.o
+lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT)	+= flash_header.o
diff --git a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h
new file mode 100644
index 0000000000..3bcb470b74
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h
@@ -0,0 +1,103 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+
+#define L2CC_AUX_CTL_CONFIG	0x00030024
+
+#define AIPS_MPR_CONFIG		0x77777777
+#define AIPS_OPACR_CONFIG	0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG		0x00302154
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG	0x00000010
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG	0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG	0x00000040
+
+#define DBG_BASE_ADDR		WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG	0x0000D843
+#define DBG_CSCR_L_CONFIG	0x22252521
+#define DBG_CSCR_A_CONFIG	0x22220A00
+
+#define CCM_CCMR_CONFIG		0x003F4208
+#define CCM_PDR0_CONFIG		0x00821000
+
+#define PLL_BRM_OFFSET	31
+#define PLL_PD_OFFSET	26
+#define PLL_MFD_OFFSET	16
+#define PLL_MFI_OFFSET	10
+
+#define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
+#define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
+#define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
+#define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+/*MEMORY SETING*/
+#define ESDCTL_0x92220000	0x92220000
+#define ESDCTL_0xA2220000	0xA2220000
+#define ESDCTL_0xB2220000	0xB2220000
+#define ESDCTL_0x82228080 	0x82228080
+
+#define ESDCTL_PRECHARGE	0x00000400
+
+#define ESDCTL_MDDR_CONFIG 	0x007FFC3F
+#define ESDCTL_MDDR_MR		0x00000033
+#define ESDCTL_MDDR_EMR		0x02000000
+
+#define ESDCTL_DDR2_CONFIG 	0x007FFC3F
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5	0x00F49F00
+#endif				/* __BOARD_MX35_3STACK_H */
diff --git a/arch/arm/boards/freescale-mx35-3ds/env/config b/arch/arm/boards/freescale-mx35-3ds/env/config
new file mode 100644
index 0000000000..af2fb6b2bc
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/env/config
@@ -0,0 +1,51 @@
+#!/bin/sh
+
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-${global.hostname}.$rootfs_type
+
+kernelimage=zImage-${global.hostname}
+#kernelimage=uImage-${global.hostname}
+#kernelimage=Image-${global.hostname}
+#kernelimage=Image-${global.hostname}.lzo
+
+if [ -n $user ]; then
+	kernelimage="$user"-"$kernelimage"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
+	rootfsimage="$user"-"$rootfsimage"
+else
+	nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc0,115200"
+
+nor_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)"
+rootfs_mtdblock_nor=3
+
+nand_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)"
+rootfs_mtdblock_nand=7
+nand_device=mxc_nand
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/freescale-mx35-3ds/flash_header.c b/arch/arm/boards/freescale-mx35-3ds/flash_header.c
new file mode 100644
index 0000000000..076b816491
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/flash_header.c
@@ -0,0 +1,72 @@
+#include <common.h>
+#include <mach/imx-flash-header.h>
+#include <mach/imx35-regs.h>
+#include <asm/barebox-arm-head.h>
+
+void __naked __flash_header_start go(void)
+{
+	barebox_arm_head();
+}
+
+struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
+	{ .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, },
+	{ .ptr_type = 4, .addr = 0xB8002054, .val = 0x22252521, },
+	{ .ptr_type = 4, .addr = 0xB8002058, .val = 0x22220a00, },
+
+	{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, },
+	{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000030C, },
+
+	{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
+	{ .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, },
+
+	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
+	{ .ptr_type = 4, .addr = 0xB8001008, .val = 0x92220000, },
+
+	{ .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, },
+	{ .ptr_type = 4, .addr = 0x90000400, .val = 0x12345678, },
+
+	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
+	{ .ptr_type = 4, .addr = 0xB8001008, .val = 0xA2220000, },
+
+	{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
+	{ .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, },
+
+	{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
+	{ .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, },
+
+	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
+	{ .ptr_type = 4, .addr = 0xB8001008, .val = 0xB2220000, },
+
+	{ .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },
+	{ .ptr_type = 1, .addr = 0x90000233, .val = 0xda, },
+
+	{ .ptr_type = 1, .addr = 0x82000780, .val = 0xda, },
+	{ .ptr_type = 1, .addr = 0x92000780, .val = 0xda, },
+
+	{ .ptr_type = 1, .addr = 0x82000400, .val = 0xda, },
+	{ .ptr_type = 1, .addr = 0x92000400, .val = 0xda, },
+
+	{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82226080, },
+	{ .ptr_type = 4, .addr = 0xB8001008, .val = 0x82226080, },
+
+	{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
+	{ .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, },
+
+	{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, },
+};
+
+
+struct imx_flash_header __flash_header_section flash_header = {
+	.app_code_jump_vector	= DEST_BASE + 0x1000,
+	.app_code_barker	= APP_CODE_BARKER,
+	.app_code_csf		= 0,
+	.dcd_ptr_ptr		= FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
+	.super_root_key		= 0,
+	.dcd			= FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
+	.app_dest		= DEST_BASE,
+	.dcd_barker		= DCD_BARKER,
+	.dcd_block_len		= sizeof(dcd_entry),
+};
+
+unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;
+
diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
new file mode 100644
index 0000000000..6d37f35a2e
--- /dev/null
+++ b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
@@ -0,0 +1,262 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/imx35-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/esdctl.h>
+#include <asm/cache-l2x0.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/barebox-arm-head.h>
+
+#include "board-mx35_3stack.h"
+
+#define CSD0_BASE_ADDR		0x80000000
+#define CSD1_BASE_ADDR		0x90000000
+#define ESDCTL_BASE_ADDR	0xB8001000
+
+#define writel(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	str		r1,	[r0];
+
+#define writeb(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	strb		r1,	[r0];
+
+/* Assuming 24MHz input clock */
+#define MPCTL_PARAM_399	(IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532	((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+#define PPCTL_PARAM_300	(IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
+
+	.section ".text_bare_init","ax"
+
+ARM_PPMRR:		.word	0x40000015
+L2CACHE_PARAM:		.word	0x00030024
+CCM_CCMR_W:		.word	0x003F4208
+CCM_PDR0_W:		.word	0x00001000
+MPCTL_PARAM_399_W:	.word	MPCTL_PARAM_399
+MPCTL_PARAM_532_W:	.word	MPCTL_PARAM_532
+PPCTL_PARAM_W:		.word	PPCTL_PARAM_300
+CCM_BASE_ADDR_W:	.word	MX35_CCM_BASE_ADDR
+
+.globl barebox_arm_reset_vector
+barebox_arm_reset_vector:
+	bl	arm_cpu_lowlevel_init
+
+	mrc	15, 0, r1, c1, c0, 0
+
+	mrc	15, 0, r0, c1, c0, 1
+	orr	r0, r0, #7
+	mcr	15, 0, r0, c1, c0, 1
+
+	orr	r1, r1, #(1 << 11)		/* Flow prediction (Z) */
+	orr	r1, r1, #(1 << 22)		/* unaligned accesses */
+	orr	r1, r1, #(1 << 21)		/* Low Int Latency */
+
+	mcr	15, 0, r1, c1, c0, 0
+
+	mov	r0, #0
+	mcr	15, 0, r0, c15, c2, 4
+
+	/*
+	 * Branch predicition is now enabled. Flush the BTAC to ensure a valid
+	 * starting point. Don't flush BTAC while it is disabled to avoid
+	 * ARM1136 erratum 408023.
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 6		/* flush entire BTAC */
+
+	mov	r0, #0
+	mcr	15, 0, r0, c7, c7, 0		/* invalidate I cache and D cache */
+	mcr	15, 0, r0, c8, c7, 0		/* invalidate TLBs */
+	mcr	15, 0, r0, c7, c10, 4		/* Drain the write buffer */
+
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr	r0, ARM_PPMRR			/* start from AIPS 2GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+
+/*
+ * End of ARM1136 init
+ */
+	ldr	r0, CCM_BASE_ADDR_W
+
+	ldr	r2, CCM_CCMR_W
+	str	r2, [r0, #MX35_CCM_CCMR]
+
+	ldr	r3, MPCTL_PARAM_532_W		/* consumer path*/
+
+	/* Set MPLL, arm clock and ahb clock */
+	str	r3, [r0, #MX35_CCM_MPCTL]
+
+	ldr	r1, PPCTL_PARAM_W
+	str	r1, [r0, #MX35_CCM_PPCTL]
+
+	ldr	r1, CCM_PDR0_W
+	str	r1, [r0, #MX35_CCM_PDR0]
+
+	ldr	r1, [r0, #MX35_CCM_CGR0]
+	orr	r1, r1, #0x00300000
+	str	r1, [r0, #MX35_CCM_CGR0]
+
+	ldr	r1, [r0, #MX35_CCM_CGR1]
+	orr	r1, r1, #0x00000C00
+	orr	r1, r1, #0x00000003
+	str	r1, [r0, #MX35_CCM_CGR1]
+
+	/* Skip SDRAM initialization if we run from RAM */
+	cmp	pc, #CSD0_BASE_ADDR
+	bls	1f
+	cmp	pc, #CSD1_BASE_ADDR
+	bhi	1f
+
+	b	imx35_barebox_entry
+
+1:
+	ldr	r0, =ESDCTL_BASE_ADDR
+	mov	r3, #0x2000
+	str	r3, [r0, #0x0]
+	str	r3, [r0, #0x8]
+
+	/* ip(r12) has used to save lr register in upper calling */
+	mov	fp, lr
+
+	/* setup bank 0 */
+	mov	r5, #0x00
+	mov	r2, #0x00
+	mov	r1, #MX35_CSD0_BASE_ADDR
+	bl	setup_sdram_bank
+
+	/* setup bank 1 */
+	mov	r5, #0x00
+	mov	r2, #0x00
+	mov	r1, #MX35_CSD1_BASE_ADDR
+	bl	setup_sdram_bank
+
+	mov	lr, fp
+
+	ldr	r3, =ESDCTL_DELAY_LINE5
+	str	r3, [r0, #0x30]
+
+#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
+	/* Setup a temporary stack in internal SRAM */
+	ldr	sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
+
+	mov	r0, #0
+	b	imx35_barebox_boot_nand_external
+#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
+
+	b	imx35_barebox_entry
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base
+ */
+setup_sdram_bank:
+	mov	r3, #0xE			/* 0xA + 0x4 */
+	tst	r2, #0x1
+	orreq	r3, r3, #0x300			/* DDR2 */
+	str	r3, [r0, #0x10]
+	bic	r3, r3, #0x00A
+	str	r3, [r0, #0x10]
+	beq	2f
+
+	mov	r3, #0x20000
+1:	subs	r3, r3, #1
+	bne	1b
+
+2:	tst	r2, #0x1
+	ldreq	r3, =ESDCTL_DDR2_CONFIG
+	ldrne	r3, =ESDCTL_MDDR_CONFIG
+	cmp	r1, #CSD1_BASE_ADDR
+	strlo	r3, [r0, #0x4]
+	strhs	r3, [r0, #0xC]
+
+	ldr	r3, =ESDCTL_0x92220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	ldr	r4, =ESDCTL_PRECHARGE
+	strb	r3, [r1, r4]
+
+	tst	r2, #0x1
+	bne	skip_set_mode
+
+	cmp	r1, #CSD1_BASE_ADDR
+	ldr	r3, =ESDCTL_0xB2220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	ldr	r4, =ESDCTL_DDR2_EMR2
+	strb	r3, [r1, r4]
+	ldr	r4, =ESDCTL_DDR2_EMR3
+	strb	r3, [r1, r4]
+	ldr	r4, =ESDCTL_DDR2_EN_DLL
+	strb	r3, [r1, r4]
+	ldr	r4, =ESDCTL_DDR2_RESET_DLL
+	strb	r3, [r1, r4]
+
+	ldr	r3, =ESDCTL_0x92220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	ldr	r4, =ESDCTL_PRECHARGE
+	strb	r3, [r1, r4]
+
+skip_set_mode:
+	cmp	r1, #CSD1_BASE_ADDR
+	ldr	r3, =ESDCTL_0xA2220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	mov	r3, #0xDA
+	strb	r3, [r1]
+	strb	r3, [r1]
+
+	ldr	r3, =ESDCTL_0xB2220000
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+	tst	r2, #0x1
+	ldreq	r4, =ESDCTL_DDR2_MR
+	ldrne	r4, =ESDCTL_MDDR_MR
+	mov	r3, #0xDA
+	strb	r3, [r1, r4]
+	ldreq	r4, =ESDCTL_DDR2_OCD_DEFAULT
+	streqb	r3, [r1, r4]
+	ldreq	r4, =ESDCTL_DDR2_EN_DLL
+	ldrne	r4, =ESDCTL_MDDR_EMR
+	strb	r3, [r1, r4]
+
+	cmp	r1, #CSD1_BASE_ADDR
+	ldr	r3, =ESDCTL_0x82228080
+	strlo	r3, [r0, #0x0]
+	strhs	r3, [r0, #0x8]
+
+	tst	r2, #0x1
+	moveq	r4, #0x20000
+	movne	r4, #0x200
+1:	subs	r4, r4, #1
+	bne	1b
+
+	str	r3, [r1, #0x100]
+	ldr	r4, [r1, #0x100]
+	cmp	r3, r4
+	movne	r3, #1
+	moveq	r3, #0
+
+	mov	pc, lr