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authorSascha Hauer <s.hauer@pengutronix.de>2019-07-16 12:41:49 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-07-16 15:16:11 +0200
commitea8981915e1d3dffe651e8ce3049cd1f707c96a1 (patch)
tree605a24e2ed9d0658ba585be7e62628a7dd366a7f /arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
parent1cd4bfe5f6a1766893e15199f37a8ec595a3e9a2 (diff)
downloadbarebox-ea8981915e1d3dffe651e8ce3049cd1f707c96a1.tar.gz
barebox-ea8981915e1d3dffe651e8ce3049cd1f707c96a1.tar.xz
ARM: nxp-imx8mq-evk: Do setup_c() before accessing global variables
The lowlevel board code accesses global variables, so call relocate_to_current_adr() / setup_c() to make sure we have a valid C environment. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/nxp-imx8mq-evk/lowlevel.c')
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/lowlevel.c54
1 files changed, 31 insertions, 23 deletions
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 6451e5d414..e3fdc64edf 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -67,30 +67,8 @@ static void nxp_imx8mq_evk_sram_setup(void)
BUG_ON(ret);
}
-/*
- * Power-on execution flow of start_nxp_imx8mq_evk() might not be
- * obvious for a very first read, so here's, hopefully helpful,
- * summary:
- *
- * 1. MaskROM uploads PBL into OCRAM and that's where this function is
- * executed for the first time
- *
- * 2. DDR is initialized and full i.MX image is loaded to the
- * beginning of RAM
- *
- * 3. start_nxp_imx8mq_evk, now in RAM, is executed again
- *
- * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
- *
- * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
- * executing start_nxp_imx8mq_evk() the third time
- *
- * 6. Standard barebox boot flow continues
- */
-ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
+static __noreturn noinline void nxp_imx8mq_evk_start(void)
{
- imx8mq_cpu_lowlevel_init();
-
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
@@ -125,3 +103,33 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
imx8mq_barebox_entry(__dtb_imx8mq_evk_start);
}
+/*
+ * Power-on execution flow of start_nxp_imx8mq_evk() might not be
+ * obvious for a very first read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ * executed for the first time
+ *
+ * 2. DDR is initialized and full i.MX image is loaded to the
+ * beginning of RAM
+ *
+ * 3. start_nxp_imx8mq_evk, now in RAM, is executed again
+ *
+ * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
+ *
+ * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * executing start_nxp_imx8mq_evk() the third time
+ *
+ * 6. Standard barebox boot flow continues
+ */
+ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
+{
+ imx8mq_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ nxp_imx8mq_evk_start();
+}
+