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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-12-18 15:22:37 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-12-20 11:43:05 +0100 |
| commit | 95f4112191363bae39323b60ac726fad41082807 (patch) | |
| tree | 5cbba9f9d69f10426548e4744082f2b1d575e8f8 /arch/arm/boards/omap343xdsp | |
| parent | 416a99135af481a335472236fc3ef1c7a17a76ad (diff) | |
| download | barebox-95f4112191363bae39323b60ac726fad41082807.tar.gz barebox-95f4112191363bae39323b60ac726fad41082807.tar.xz | |
ARM omap3: Add change OMAP_ prefix to OMAP3_ for registers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/omap343xdsp')
| -rw-r--r-- | arch/arm/boards/omap343xdsp/board.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c index 6de86f4326..eb752ff027 100644 --- a/arch/arm/boards/omap343xdsp/board.c +++ b/arch/arm/boards/omap343xdsp/board.c @@ -94,54 +94,54 @@ pure_initcall(sdp343x_board_init); static void sdrc_init(void) { /* Issue SDRC Soft reset */ - writel(0x12, SDRC_REG(SYSCONFIG)); + writel(0x12, OMAP3_SDRC_REG(SYSCONFIG)); /* Wait until Reset complete */ - while ((readl(SDRC_REG(STATUS)) & 0x1) == 0); + while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0); /* SDRC to normal mode */ - writel(0x10, SDRC_REG(SYSCONFIG)); + writel(0x10, OMAP3_SDRC_REG(SYSCONFIG)); /* SDRC Sharing register */ /* 32-bit SDRAM on data lane [31:0] - CS0 */ /* pin tri-stated = 1 */ - writel(0x00000100, SDRC_REG(SHARING)); + writel(0x00000100, OMAP3_SDRC_REG(SHARING)); /* ----- SDRC_REG(CS0 Configuration --------- */ /* SDRC_REG(MCFG0 register */ - writel(0x02584019, SDRC_REG(MCFG_0)); + writel(0x02584019, OMAP3_SDRC_REG(MCFG_0)); /* SDRC_REG(RFR_CTRL0 register */ - writel(0x0003DE01, SDRC_REG(RFR_CTRL_0)); + writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0)); /* SDRC_REG(ACTIM_CTRLA0 register */ - writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0)); + writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0)); /* SDRC_REG(ACTIM_CTRLB0 register */ - writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0)); + writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0)); /* Disble Power Down of CKE cuz of 1 CKE on combo part */ - writel(0x00000081, SDRC_REG(POWER)); + writel(0x00000081, OMAP3_SDRC_REG(POWER)); /* SDRC_REG(Manual command register */ /* NOP command */ - writel(0x00000000, SDRC_REG(MANUAL_0)); + writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0)); /* Precharge command */ - writel(0x00000001, SDRC_REG(MANUAL_0)); + writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0)); /* Auto-refresh command */ - writel(0x00000002, SDRC_REG(MANUAL_0)); + writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0)); /* Auto-refresh command */ - writel(0x00000002, SDRC_REG(MANUAL_0)); + writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0)); /* SDRC MR0 register */ /* CAS latency = 3 */ /* Write Burst = Read Burst */ /* Serial Mode */ - writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */ + writel(0x00000032, OMAP3_SDRC_REG(MR_0)); /* Burst length =4 */ /* SDRC DLLA control register */ /* Enable DLL A */ - writel(0x0000000A, SDRC_REG(DLLA_CTRL)); + writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL)); /* wait until DLL is locked */ - while ((readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0); + while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0); return; } |