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| author | Teresa Gámez <t.gamez@phytec.de> | 2011-08-23 14:30:27 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-08-23 14:45:19 +0200 |
| commit | 140f7dd719a02605ce8b69cd963546c5ab84e22d (patch) | |
| tree | 198d4505bf4f860cdd8eb060f437f22891c5c5c4 /arch/arm/boards/pcm043 | |
| parent | 8ddfe5911d0806ad41570a78ed71b2f98b6ec04c (diff) | |
| download | barebox-140f7dd719a02605ce8b69cd963546c5ab84e22d.tar.gz barebox-140f7dd719a02605ce8b69cd963546c5ab84e22d.tar.xz | |
ARM pcm043: Check silicon revision to set up cpu freq correct
Some older pcm043 only work correct when cpu frequency is set up
to 399MHz. All modules with revision >= 1315.4 are equipped
with a i.MX35 TO2.1 and do run with 532MHz.
Check the silicon revision and set up the frequency accordingly.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/pcm043')
| -rw-r--r-- | arch/arm/boards/pcm043/lowlevel.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index eff96f9777..17d3cd71e9 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -37,6 +37,11 @@ #define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) #define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) +#define IMX35_CHIP_REVISION_2_1 0x11 + +#define CCM_PDR0_399 0x00011000 +#define CCM_PDR0_532 0x00001000 + #ifdef CONFIG_NAND_IMX_BOOT static void __bare_init __naked insdram(void) { @@ -111,7 +116,13 @@ void __bare_init __naked board_init_lowlevel(void) writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); - writel(0x00001000, ccm_base + CCM_PDR0); + + /* Check silicon revision and use 532MHz if >=2.1 */ + r = readl(IMX_IIM_BASE + 0x24); + if (r >= IMX35_CHIP_REVISION_2_1) + writel(CCM_PDR0_532, ccm_base + CCM_PDR0); + else + writel(CCM_PDR0_399, ccm_base + CCM_PDR0); r = readl(ccm_base + CCM_CGR0); r |= 0x00300000; |