ARM: rename boards to more consistent naming

This renames the Freescale and Phytec board directories and defconfig
files to a common naming scheme. The board directories are named
<vendor>-<board> and the defconfig files are named
<vendor>-<board>_defconfig. Also the DataModul realq7 is renamed to its
Marketing Name eDM-QMX6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 263 insertions, 0 deletions

diff --git a/arch/arm/boards/phytec-phycard-imx27/Makefile b/arch/arm/boards/phytec-phycard-imx27/Makefile
new file mode 100644
index 0000000000..34492bb127
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx27/Makefile
@@ -0,0 +1,3 @@
+
+lwl-y += lowlevel.o
+obj-y += pca100.o
diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
new file mode 100644
index 0000000000..5b3bdafa71
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -0,0 +1,103 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <config.h>
+#include <asm/barebox-arm-head.h>
+#include <mach/imx27-regs.h>
+#include <mach/imx-pll.h>
+#include <mach/esdctl.h>
+#include <mach/imx-nand.h>
+
+#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
+
+static void sdram_init(void)
+{
+	int i;
+
+	/*
+	 * DDR on CSD0
+	 */
+	/* Enable DDR SDRAM operation */
+	writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+
+	/* Set the driving strength   */
+	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
+	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
+	writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
+	writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
+	writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
+
+	/* Initial reset */
+	writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
+	writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
+
+	/* precharge CSD0 all banks */
+	writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
+			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+	writel(0x00000000, 0xa0000f00);	/* CSD0 precharge address (A10 = 1) */
+	writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
+			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+
+	for (i = 0; i < 8; i++)
+		writel(0, 0xa0000f00);
+
+	writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
+			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+	writeb(0xda, 0xa0000033);
+	writeb(0xff, 0xa1000000);
+
+	writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
+			ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
+			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
+}
+
+void __bare_init __naked barebox_arm_reset_vector(void)
+{
+	unsigned long r;
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
+
+	/* ahb lite ip interface */
+	writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
+	writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
+	writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
+	writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
+
+	/* Skip SDRAM initialization if we run from RAM */
+        r = get_pc();
+        if (r > 0xa0000000 && r < 0xc0000000)
+                imx27_barebox_entry(0);
+
+	/* 399 MHz */
+	writel(IMX_PLL_PD(0) |
+		 IMX_PLL_MFD(51) |
+		 IMX_PLL_MFI(7) |
+		 IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0);
+
+	/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
+	writel(IMX_PLL_PD(1) |
+		 IMX_PLL_MFD(12) |
+		 IMX_PLL_MFI(9) |
+		 IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0);
+
+	writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
+		MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
+		MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
+		MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
+		MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
+		MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
+		MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
+		MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
+
+	sdram_init();
+
+	imx27_barebox_boot_nand_external(0);
+}
diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c
new file mode 100644
index 0000000000..4b355bcc6a
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/imx27-regs.h>
+#include <fec.h>
+#include <gpio.h>
+#include <sizes.h>
+#include <asm/armlinux.h>
+#include <asm/sections.h>
+#include <generated/mach-types.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <nand.h>
+#include <spi/spi.h>
+#include <io.h>
+#include <mach/imx-nand.h>
+#include <mach/imx-pll.h>
+#include <mach/imxfb.h>
+#include <gpio.h>
+#include <asm/mmu.h>
+#include <usb/ulpi.h>
+#include <mach/bbu.h>
+#include <mach/iomux-mx27.h>
+#include <mach/devices-imx27.h>
+
+static void pca100_usb_register(void)
+{
+	mdelay(10);
+
+	gpio_direction_output(GPIO_PORTB + 24, 0);
+	gpio_direction_output(GPIO_PORTB + 23, 0);
+
+	mdelay(10);
+
+	ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL);
+	ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
+	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
+}
+
+static void pca100_usb_init(void)
+{
+	u32 reg;
+
+	reg = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
+	reg &= ~((3 << 21) | 1);
+	reg |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
+	writel(reg, MX27_USB_OTG_BASE_ADDR + 0x600);
+
+	/*
+	 * switch usbotg and usbh2 to ulpi mode. Do this *before*
+	 * the iomux setup to prevent funny hardware bugs from
+	 * triggering. Also, do this even when USB support is
+	 * disabled to give Linux USB support a good start.
+	 */
+	reg = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
+	reg &= ~(3 << 30);
+	reg |= 2 << 30;
+	writel(reg, MX27_USB_OTG_BASE_ADDR + 0x584);
+
+	reg = readl(MX27_USB_OTG_BASE_ADDR + 0x184);
+	reg &= ~(3 << 30);
+	reg |= 2 << 30;
+	writel(reg, MX27_USB_OTG_BASE_ADDR + 0x184);
+
+	/* disable the usb phys */
+	imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN);
+	gpio_direction_output(GPIO_PORTB + 23, 1);
+	imx_gpio_mode((GPIO_PORTB | 24) | GPIO_GPIO | GPIO_IN);
+	gpio_direction_output(GPIO_PORTB + 24, 1);
+}
+
+static int pca100_devices_init(void)
+{
+	int i;
+	unsigned int mode[] = {
+		/* USB host 2 */
+		PA0_PF_USBH2_CLK,
+		PA1_PF_USBH2_DIR,
+		PA2_PF_USBH2_DATA7,
+		PA3_PF_USBH2_NXT,
+		PA4_PF_USBH2_STP,
+		PD19_AF_USBH2_DATA4,
+		PD20_AF_USBH2_DATA3,
+		PD21_AF_USBH2_DATA6,
+		PD22_AF_USBH2_DATA0,
+		PD23_AF_USBH2_DATA2,
+		PD24_AF_USBH2_DATA1,
+		PD26_AF_USBH2_DATA5,
+		PC7_PF_USBOTG_DATA5,
+		PC8_PF_USBOTG_DATA6,
+		PC9_PF_USBOTG_DATA0,
+		PC10_PF_USBOTG_DATA2,
+		PC11_PF_USBOTG_DATA1,
+		PC12_PF_USBOTG_DATA4,
+		PC13_PF_USBOTG_DATA3,
+		PE0_PF_USBOTG_NXT,
+		PE1_PF_USBOTG_STP,
+		PE2_PF_USBOTG_DIR,
+		PE24_PF_USBOTG_CLK,
+		PE25_PF_USBOTG_DATA7,
+	};
+
+	pca100_usb_init();
+
+	/* initizalize gpios */
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+	if (IS_ENABLED(CONFIG_USB))
+		pca100_usb_register();
+
+	imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
+			BBU_HANDLER_FLAG_DEFAULT);
+
+	armlinux_set_architecture(2149);
+
+	return 0;
+}
+
+device_initcall(pca100_devices_init);
+
+static int pca100_console_init(void)
+{
+	barebox_set_model("Phytec phyCARD-i.MX27");
+	barebox_set_hostname("phycard-imx27");
+
+	return 0;
+}
+
+console_initcall(pca100_console_init);
diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.dox b/arch/arm/boards/phytec-phycard-imx27/pca100.dox
new file mode 100644
index 0000000000..9b17674a21
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx27/pca100.dox
@@ -0,0 +1,8 @@
+/** @page pcm038 Phytec's phyCORE-i.MX27
+
+This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with:
+
+- up to 32MiB NOR type Flash Memory
+- 32MiB synchronous dynamic RAM
+
+*/