imx6: Add support for phyCARD-i.MX6

Add support for Phytec phyCARD-i.MX6.
	- 1GB RAM on two banks
	- 1GB RAM on one bank
	- 2GB RAM on two banks

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

10 files changed, 298 insertions, 0 deletions

diff --git a/arch/arm/boards/phytec-phycard-imx6/Makefile b/arch/arm/boards/phytec-phycard-imx6/Makefile
new file mode 100644
index 0000000000..01c7a259e9
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/phytec-phycard-imx6/board.c b/arch/arm/boards/phytec-phycard-imx6/board.c
new file mode 100644
index 0000000000..6ed431adcd
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/board.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2014 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <environment.h>
+#include <bootsource.h>
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <of.h>
+
+#include <mach/bbu.h>
+#include <mach/imx6.h>
+
+static int phytec_pcaaxl3_init(void)
+{
+	if (!of_machine_is_compatible("phytec,imx6q-pcaaxl3"))
+		return 0;
+
+	switch (bootsource_get()) {
+	case BOOTSOURCE_MMC:
+		of_device_enable_path("/chosen/environment-sd");
+		break;
+	default:
+	case BOOTSOURCE_NAND:
+		of_device_enable_path("/chosen/environment-nand");
+		break;
+	}
+
+	imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
+
+	return 0;
+}
+device_initcall(phytec_pcaaxl3_init);
+
+static int phytec_pcaaxl3_core_init(void)
+{
+	if (!of_machine_is_compatible("phytec,imx6q-pcaaxl3"))
+		return 0;
+
+	imx6_init_lowlevel();
+
+	return 0;
+}
+postcore_initcall(phytec_pcaaxl3_core_init);
diff --git a/arch/arm/boards/phytec-phycard-imx6/env/boot/nand b/arch/arm/boards/phytec-phycard-imx6/env/boot/nand
new file mode 100644
index 0000000000..a51da9e340
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/env/boot/nand
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+        boot-menu-add-entry "$0" "Kernel:nand;rootfs:nand"
+        exit
+fi
+
+global.bootm.image="/dev/nand0.kernel.bb"
+#global.bootm.oftree="/env/oftree"
+bootargs-ip
+global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs"
+
diff --git a/arch/arm/boards/phytec-phycard-imx6/env/boot/sd-ext3 b/arch/arm/boards/phytec-phycard-imx6/env/boot/sd-ext3
new file mode 100644
index 0000000000..fa1e9d68c9
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/env/boot/sd-ext3
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+        boot-menu-add-entry "$0" "MMC (ext3)"
+        exit
+fi
+
+global.bootm.image="/mnt/kernel/linuximage"
+#global.bootm.oftree="/boot/oftree"
+bootargs-ip
+global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
diff --git a/arch/arm/boards/phytec-phycard-imx6/env/config-board b/arch/arm/boards/phytec-phycard-imx6/env/config-board
new file mode 100644
index 0000000000..44008aa3e7
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/env/config-board
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=phyCARD-i.MX6
+global.linux.bootargs.base="console=ttymxc2,115200"
diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg
new file mode 100644
index 0000000000..481e085477
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg
@@ -0,0 +1,7 @@
+#define SETUP_1GIB_2GIB			\
+	wm 32 0x021b000c 0x54597955;	\
+	wm 32 0x021b0030 0x00591023;	\
+	wm 32 0x021b0040 0x00000027;	\
+	wm 32 0x021b0000 0x831a0000
+
+#include "flash-header-phytec-pcaaxl3.h"
diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
new file mode 100644
index 0000000000..b21bd894b0
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg
@@ -0,0 +1,7 @@
+#define SETUP_1GIB_2GIB			\
+	wm 32 0x021b000c 0x3a3f7975;	\
+	wm 32 0x021b0030 0x003f1023;	\
+	wm 32 0x021b0040 0x00000017;	\
+	wm 32 0x021b0000 0xc21a0000
+
+#include "flash-header-phytec-pcaaxl3.h"
diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
new file mode 100644
index 0000000000..858b6d754b
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg
@@ -0,0 +1,8 @@
+
+#define SETUP_1GIB_2GIB			\
+	wm 32 0x021b000c 0x54597955;	\
+	wm 32 0x021b0030 0x00591023;	\
+	wm 32 0x021b0040 0x00000027;	\
+	wm 32 0x021b0000 0xc31a0000
+
+#include "flash-header-phytec-pcaaxl3.h"
diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h
new file mode 100644
index 0000000000..aecaf160bb
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h
@@ -0,0 +1,97 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+wm 32 0x020e05a8 0x00000028
+wm 32 0x020e05b0 0x00000028
+wm 32 0x020e0524 0x00000028
+wm 32 0x020e051c 0x00000028
+wm 32 0x020e0518 0x00000028
+wm 32 0x020e050c 0x00000028
+wm 32 0x020e05b8 0x00000028
+wm 32 0x020e05c0 0x00000028
+wm 32 0x020e05ac 0x00000028
+wm 32 0x020e05b4 0x00000028
+wm 32 0x020e0528 0x00000028
+wm 32 0x020e0520 0x00000028
+wm 32 0x020e0514 0x00000028
+wm 32 0x020e0510 0x00000028
+wm 32 0x020e05bc 0x00000028
+wm 32 0x020e05c4 0x00000028
+wm 32 0x020e056c 0x00000028
+wm 32 0x020e0578 0x00000028
+wm 32 0x020e0588 0x00000028
+wm 32 0x020e0594 0x00000028
+wm 32 0x020e057c 0x00000028
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00000028
+wm 32 0x020e05a0 0x00000028
+wm 32 0x020e0784 0x00000028
+wm 32 0x020e0788 0x00000028
+wm 32 0x020e0794 0x00000028
+wm 32 0x020e079c 0x00000028
+wm 32 0x020e07a0 0x00000028
+wm 32 0x020e07a4 0x00000028
+wm 32 0x020e07a8 0x00000028
+wm 32 0x020e0748 0x00000028
+wm 32 0x020e074c 0x00000028
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000028
+wm 32 0x020e0798 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00091740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b0010 0xff328f64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+
+SETUP_1GIB_2GIB
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x00048039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00007800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b083c 0x4350035e
+wm 32 0x021b0840 0x035c0358
+wm 32 0x021b483c 0x436e0376
+wm 32 0x021b4840 0x03770352
+wm 32 0x021b0848 0x3c333436
+wm 32 0x021b4848 0x35332f3b
+wm 32 0x021b0850 0x37363e39
+wm 32 0x021b4850 0x432f433d
+wm 32 0x021b080c 0x0013001b
+wm 32 0x021b0810 0x003b0034
+wm 32 0x021b480c 0x0037004b
+wm 32 0x021b4810 0x004b0055
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020e0010 0xf00000ff
+wm 32 0x020e0018 0x007f007f
+wm 32 0x020e001c 0x007f007f
+wm 32 0x020c8000 0x80002021
diff --git a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
new file mode 100644
index 0000000000..14df18f835
--- /dev/null
+++ b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2014 Christian Hemp <c.hemp@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <debug_ll.h>
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/imx6.h>
+
+static inline void setup_uart(void)
+{
+	void __iomem *ccmbase = IOMEM(MX6_CCM_BASE_ADDR);
+	void __iomem *uartbase = IOMEM(MX6_UART3_BASE_ADDR);
+	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+
+	writel(0x4, iomuxbase + 0x01f8);
+
+	writel(0xffffffff, ccmbase + 0x68);
+	writel(0xffffffff, ccmbase + 0x6c);
+	writel(0xffffffff, ccmbase + 0x70);
+	writel(0xffffffff, ccmbase + 0x74);
+	writel(0xffffffff, ccmbase + 0x78);
+	writel(0xffffffff, ccmbase + 0x7c);
+	writel(0xffffffff, ccmbase + 0x80);
+
+	writel(0x00000000, uartbase + 0x80);
+	writel(0x00004027, uartbase + 0x84);
+	writel(0x00000704, uartbase + 0x88);
+	writel(0x00000a81, uartbase + 0x90);
+	writel(0x0000002b, uartbase + 0x9c);
+	writel(0x00013880, uartbase + 0xb0);
+	writel(0x0000047f, uartbase + 0xa4);
+	writel(0x0000c34f, uartbase + 0xa8);
+	writel(0x00000001, uartbase + 0x80);
+
+	putc_ll('>');
+}
+
+extern char __dtb_imx6q_phytec_pbaa03_start[];
+
+static void __noreturn start_imx6q_phytec_pbaa03_common(uint32_t size)
+{
+	uint32_t fdt;
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = (uint32_t)__dtb_imx6q_phytec_pbaa03_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, size, fdt);
+}
+
+ENTRY_FUNCTION(start_phytec_pbaa03_1gib, r0, r1, r2)
+{
+	start_imx6q_phytec_pbaa03_common(SZ_1G);
+}
+
+ENTRY_FUNCTION(start_phytec_pbaa03_1gib_1bank, r0, r1, r2)
+{
+	start_imx6q_phytec_pbaa03_common(SZ_1G);
+}
+
+ENTRY_FUNCTION(start_phytec_pbaa03_2gib, r0, r1, r2)
+{
+	start_imx6q_phytec_pbaa03_common(SZ_2G);
+}