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authorJan Luebbe <jlu@pengutronix.de>2012-09-24 10:18:34 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2012-09-27 19:30:04 +0200
commitfaf7b7af6e51a33b88453821d792c89a84f72b1d (patch)
treebff70e6a71339e4d62e90c23ead1fc351effc89a /arch/arm/boards/scb9328
parentcc1602604d1654991f3ce02b664178b3e672afe7 (diff)
downloadbarebox-faf7b7af6e51a33b88453821d792c89a84f72b1d.tar.gz
barebox-faf7b7af6e51a33b88453821d792c89a84f72b1d.tar.xz
ARM: give boards control of the reset entry point
On some SoCs (for example AM35xx), the ROM bootloader passes useful information in r0 when jumping to barebox. To avoid overwriting this in the generic reset code, we introduce common_reset as a C function and as an assembler macro. This is then called form the reset entry point (either in common or in board code). This patch is based on code by Sascha Hauer <s.hauer@pengutronix.de>. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/scb9328')
-rw-r--r--arch/arm/boards/scb9328/lowlevel_init.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S
index 5b024286bb..087e8e6b9f 100644
--- a/arch/arm/boards/scb9328/lowlevel_init.S
+++ b/arch/arm/boards/scb9328/lowlevel_init.S
@@ -19,6 +19,7 @@
*/
#include <mach/imx-regs.h>
+#include <asm/barebox-arm-head.h>
#define CPU200
@@ -81,10 +82,10 @@
ldr r1, =val; \
str r1, [r0];
-.globl board_init_lowlevel
-board_init_lowlevel:
+.globl reset
+reset:
- mov r10, lr
+ common_reset r0
/* Change PERCLK1DIV to 14 ie 14+1 */
writel(CFG_PCDR_VAL, PCDR)
@@ -156,7 +157,7 @@ board_init_lowlevel:
cmp pc, #0x09000000
bhi 1f
- mov pc,r10
+ b board_init_lowlevel_return
1:
@@ -181,4 +182,4 @@ board_init_lowlevel:
writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */
- mov pc,r10
+ b board_init_lowlevel_return