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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-10 21:02:56 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-17 20:22:02 +0200 |
| commit | 926cccc9d5aec1854951a5ede241a407d5a4b68e (patch) | |
| tree | a0df988922d56333ba71a0165fc10784928d6fc8 /arch/arm/boards/scb9328 | |
| parent | 4c53af062b38f15f6bc40c586e5760e640f5b8b1 (diff) | |
| download | barebox-926cccc9d5aec1854951a5ede241a407d5a4b68e.tar.gz barebox-926cccc9d5aec1854951a5ede241a407d5a4b68e.tar.xz | |
ARM i.MX1: Cleanup remaining unprefixed registers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/scb9328')
| -rw-r--r-- | arch/arm/boards/scb9328/lowlevel_init.S | 29 | ||||
| -rw-r--r-- | arch/arm/boards/scb9328/scb9328.c | 4 |
2 files changed, 19 insertions, 14 deletions
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index fabc89ea1e..c303d2de7e 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -82,13 +82,13 @@ reset: common_reset r0 /* Change PERCLK1DIV to 14 ie 14+1 */ - writel(CFG_PCDR_VAL, PCDR) + writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR) /* set MCU PLL Control Register 0 */ - writel(CFG_MPCTL0_VAL, MPCTL0) + writel(CFG_MPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_MPCTL0) /* set mpll restart bit */ - ldr r0, =CSCR + ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR ldr r1, [r0] orr r1,r1,#(1<<21) str r1, [r0] @@ -104,10 +104,10 @@ reset: bne 1b /* set System PLL Control Register 0 */ - writel(CFG_SPCTL0_VAL, SPCTL0) + writel(CFG_SPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_SPCTL0) /* set spll restart bit */ - ldr r0, =CSCR + ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR ldr r1, [r0] orr r1,r1,#(1<<22) str r1, [r0] @@ -122,7 +122,7 @@ reset: subs r2,r2,#1 bne 1b - writel(CFG_CSCR_VAL, CSCR) + writel(CFG_CSCR_VAL, MX1_CCM_BASE_ADDR + MX1_CSCR) /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon *this..... @@ -157,9 +157,12 @@ reset: /* SDRAM Setup */ - writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */ - writel(0x0, 0x08200000) /* Issue Precharge all Command */ - writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */ + /* Precharge cmd, CAS = 2 */ + writel(0x910a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) + /* Issue Precharge all Command */ + writel(0x0, 0x08200000) + /* Autorefresh cmd, CAS = 2 */ + writel(0xa10a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) ldr r0, =0x08000000 ldr r1, =0x0 /* Issue AutoRefresh Command */ @@ -172,8 +175,10 @@ reset: str r1, [r0] str r1, [r0] - writel(0xb10a8300, SDCTL0) - writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ - writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */ + writel(0xb10a8300, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) + /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ + writel(0x0, 0x08223000) + /* Set to Normal Mode CAS 2 */ + writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) b board_init_lowlevel_return diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index 1a85554db2..fd2758c39c 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -69,8 +69,8 @@ static int scb9328_devices_init(void) for (i = 0; i < ARRAY_SIZE(leds); i++) led_gpio_register(&leds[i]); -/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ - FMCR = 0x1; + /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ + writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR); imx1_setup_eimcs(0, 0x000F2000, 0x11110d01); imx1_setup_eimcs(1, 0x000F0a00, 0x11110601); |