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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2019-11-12 10:19:56 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-11-13 15:20:40 +0100 |
| commit | b2da7cfcd09b9731f67afcae74604c63bda6c5c0 (patch) | |
| tree | 44ecb2088f4cfba438efa83fed9b488645cb62dd /arch/arm/boards/stm32mp157c-dk2/board.c | |
| parent | a0319d2beef4789c743132fae313718f6e6a4b20 (diff) | |
| download | barebox-b2da7cfcd09b9731f67afcae74604c63bda6c5c0.tar.gz barebox-b2da7cfcd09b9731f67afcae74604c63bda6c5c0.tar.xz | |
ARM: stm32mp: dk2: don't hard-code memory size
There's new infrastructure for runtime determining RAM size. Use it so
we don't need to hard code it in PBL and board code.
Because this new infrastructure has some nested function calls, my
arm-v7a-linux-gnueabihf-gcc 9.2.1 (OSELAS.Toolchain-2019.09.0)
spills to the stack. Add stm32mp_cpu_lowlevel_init, which also sets up
a stack after barebox end so this works.
Lastly, there's no upstream device tree node for the DDR controller.
Add one in the barebox device tree, so we don't have to hardcode the
DDRCTRL address into non-pbl code that's run everywhere.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/stm32mp157c-dk2/board.c')
| -rw-r--r-- | arch/arm/boards/stm32mp157c-dk2/board.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c index f15ae0b4af..9cd5b4ee1f 100644 --- a/arch/arm/boards/stm32mp157c-dk2/board.c +++ b/arch/arm/boards/stm32mp157c-dk2/board.c @@ -6,17 +6,6 @@ #include <mach/stm32.h> #include <mach/bbu.h> -static int dk2_mem_init(void) -{ - if (!of_machine_is_compatible("st,stm32mp157c-dk2")) - return 0; - - arm_add_mem_device("ram0", STM32_DDR_BASE, SZ_512M); - - return 0; -} -mem_initcall(dk2_mem_init); - static int dk2_postcore_init(void) { if (!of_machine_is_compatible("st,stm32mp157c-dk2")) |