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authorSascha Hauer <s.hauer@pengutronix.de>2013-09-11 11:52:28 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2013-09-23 08:40:32 +0200
commite07ddb8b97b07160376245d6b45c776bafe5b286 (patch)
tree2b1434fe2ec8839db91065ad799a0cc6456fdce2 /arch/arm/boards/terasic-sockit/lowlevel.c
parent5b5f6ab6bfdd369bd2e3f968a868569c4399c374 (diff)
downloadbarebox-e07ddb8b97b07160376245d6b45c776bafe5b286.tar.gz
barebox-e07ddb8b97b07160376245d6b45c776bafe5b286.tar.xz
ARM: SoCFPGA: Add Terasic SoCkit board support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/terasic-sockit/lowlevel.c')
-rw-r--r--arch/arm/boards/terasic-sockit/lowlevel.c99
1 files changed, 99 insertions, 0 deletions
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
new file mode 100644
index 0000000000..8a1e0ce430
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -0,0 +1,99 @@
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/generic.h>
+#include <debug_ll.h>
+#include <asm/cache.h>
+#include "sdram_config.h"
+#include <mach/sdram_config.h>
+#include "pinmux_config.c"
+#include "pll_config.h"
+#include <mach/pll_config.h>
+#include "sequencer_defines.h"
+#include "sequencer_auto.h"
+#include <mach/sequencer.c>
+#include "sequencer_auto_inst_init.c"
+#include "sequencer_auto_ac_init.c"
+
+static inline void ledon(int led)
+{
+ u32 val;
+
+ val = readl(0xFF709000);
+ val |= 1 << (led + 24);
+ writel(val, 0xFF709000);
+
+ val = readl(0xFF709004);
+ val |= 1 << (led + 24);
+ writel(val, 0xFF709004);
+}
+
+static inline void ledoff(int led)
+{
+ u32 val;
+
+ val = readl(0xFF709000);
+ val &= ~(1 << (led + 24));
+ writel(val, 0xFF709000);
+
+ val = readl(0xFF709004);
+ val &= ~(1 << (led + 24));
+ writel(val, 0xFF709004);
+}
+
+extern char __dtb_socfpga_cyclone5_sockit_start[];
+
+ENTRY_FUNCTION(start_socfpga_sockit)(void)
+{
+ uint32_t fdt;
+
+ __barebox_arm_head();
+
+ arm_cpu_lowlevel_init();
+
+ fdt = (uint32_t)__dtb_socfpga_cyclone5_sockit_start - get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_1G, fdt);
+}
+
+static noinline void sockit_entry(void)
+{
+ int ret;
+
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ socfpga_lowlevel_init(&cm_default_cfg,
+ sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table));
+
+ puts_ll("lowlevel init done\n");
+ puts_ll("SDRAM setup...\n");
+
+ socfpga_sdram_mmr_init();
+
+ puts_ll("SDRAM calibration...\n");
+
+ ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
+ ac_rom_init, ac_rom_init_size);
+ if (ret)
+ hang();
+
+ puts_ll("done\n");
+
+ barebox_arm_entry(0x0, SZ_1G, 0);
+}
+
+ENTRY_FUNCTION(start_socfpga_sockit_xload)(void)
+{
+ __barebox_arm_head();
+
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16);
+
+ sockit_entry();
+}