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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-01-07 11:57:51 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-01-07 11:57:51 +0100 |
| commit | aebde15776ec4a1d876b5a332359729c0b871629 (patch) | |
| tree | 6fb2d8c97d0c878078fac0e5efec9963c6621f97 /arch/arm/boards/terasic-sockit | |
| parent | f1f5346975a6d521f0331b3f040532f2872b1f1d (diff) | |
| parent | d9774caab6bd6393bc75e24a4f5d0d677c00e71d (diff) | |
| download | barebox-aebde15776ec4a1d876b5a332359729c0b871629.tar.gz barebox-aebde15776ec4a1d876b5a332359729c0b871629.tar.xz | |
Merge branch 'for-next/socfpga'
Diffstat (limited to 'arch/arm/boards/terasic-sockit')
| -rw-r--r-- | arch/arm/boards/terasic-sockit/pll_config.h | 2 | ||||
| -rw-r--r-- | arch/arm/boards/terasic-sockit/sdram_config.h | 21 |
2 files changed, 14 insertions, 9 deletions
diff --git a/arch/arm/boards/terasic-sockit/pll_config.h b/arch/arm/boards/terasic-sockit/pll_config.h index 732f241f4a..672ce41fb7 100644 --- a/arch/arm/boards/terasic-sockit/pll_config.h +++ b/arch/arm/boards/terasic-sockit/pll_config.h @@ -54,7 +54,7 @@ * 1 = MAIN_CLK * 2 = PERIPH_CLK */ -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) #define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) diff --git a/arch/arm/boards/terasic-sockit/sdram_config.h b/arch/arm/boards/terasic-sockit/sdram_config.h index 3d6f938750..2c04b02599 100644 --- a/arch/arm/boards/terasic-sockit/sdram_config.h +++ b/arch/arm/boards/terasic-sockit/sdram_config.h @@ -1,3 +1,6 @@ +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) @@ -58,12 +61,14 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0) +#endif /*#ifndef__SDRAM_CONFIG_H*/ |