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| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-12-09 15:10:12 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-12-10 08:42:12 +0100 |
| commit | e4ab2b933a04b9a22cbcb7c558f82413a210f333 (patch) | |
| tree | fdf821debb44ac13a4c811be70b508b174fb7a8e /arch/arm/boards/terasic-sockit | |
| parent | ace667e6bba1de3c24a02c9197c6872a6d2ea94e (diff) | |
| download | barebox-e4ab2b933a04b9a22cbcb7c558f82413a210f333.tar.gz barebox-e4ab2b933a04b9a22cbcb7c558f82413a210f333.tar.xz | |
ARM: socfpga: sockit: update sdram config
This updates/changes the sdram config for the sockit to the quartus v13.1
autogenerated version.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/terasic-sockit')
| -rw-r--r-- | arch/arm/boards/terasic-sockit/sdram_config.h | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/arch/arm/boards/terasic-sockit/sdram_config.h b/arch/arm/boards/terasic-sockit/sdram_config.h index 3d6f938750..2c04b02599 100644 --- a/arch/arm/boards/terasic-sockit/sdram_config.h +++ b/arch/arm/boards/terasic-sockit/sdram_config.h @@ -1,3 +1,6 @@ +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) @@ -58,12 +61,14 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0) +#endif /*#ifndef__SDRAM_CONFIG_H*/ |