ARM: i.MX6: add support for Karo TX6X family

The Karo TX6X family consists of different i.MX6Q/DL based System-on-Modules.
Add support for the TX6u 801x modules, that have an i.MX6DL SoC.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

7 files changed, 462 insertions, 0 deletions

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index a703f1d2fc..3601a9fba1 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -109,6 +109,7 @@ obj-$(CONFIG_MACH_TX25)				+= karo-tx25/
 obj-$(CONFIG_MACH_TX28)				+= karo-tx28/
 obj-$(CONFIG_MACH_TX51)				+= karo-tx51/
 obj-$(CONFIG_MACH_TX53)				+= karo-tx53/
+obj-$(CONFIG_MACH_TX6X)				+= karo-tx6x/
 obj-$(CONFIG_MACH_UDOO)				+= udoo/
 obj-$(CONFIG_MACH_USB_A9260)			+= usb-a926x/
 obj-$(CONFIG_MACH_USB_A9263)			+= usb-a926x/
diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
new file mode 100644
index 0000000000..b5c59e3c3c
--- /dev/null
+++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
@@ -0,0 +1,101 @@
+/* MDMISC	mirroring	interleaved (row/bank/col) */
+wm 32 MX6_MMDC_P0_MDMISC		0x00000742
+check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
+
+wm 32 MX6_MMDC_P0_MDSCR			0x00008000
+check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
+
+wm 32 MX6_MMDC_P0_MDCTL			0x831a0000
+check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
+
+wm 32 MX6_MMDC_P0_MDCFG0		0x3f435333
+wm 32 MX6_MMDC_P0_MDCFG1		0x926e8a63
+wm 32 MX6_MMDC_P0_MDCFG2		0x01ff00db
+wm 32 MX6_MMDC_P0_MDRWD			0x000026d2
+wm 32 MX6_MMDC_P0_MDOR			0x00431023
+wm 32 MX6_MMDC_P0_MDOTC			0x1b333030
+wm 32 MX6_MMDC_P0_MDPDC			0x0002006d
+wm 32 MX6_MMDC_P1_MDPDC			0x0002006d
+wm 32 MX6_MMDC_P0_MDASP			0x00000027
+
+wm 32 MX6_MMDC_P0_MDSCR			0x05208030
+wm 32 MX6_MMDC_P0_MDSCR			0x00048031
+wm 32 MX6_MMDC_P0_MDSCR			0x00408032
+wm 32 MX6_MMDC_P0_MDSCR			0x00008033
+wm 32 MX6_MMDC_P0_MDREF			0x0000c000
+wm 32 MX6_MMDC_P0_MDSCR			0x00008020
+
+wm 32 MX6_MMDC_P0_MPODTCTRL		0x00022222
+wm 32 MX6_MMDC_P1_MPODTCTRL		0x00022222
+
+wm 32 MX6_MMDC_P0_MPPDCMPR2		0x00000003
+wm 32 MX6_MMDC_P0_MAPSR			0x00001007
+wm 32 MX6_MMDC_P0_MDSCR			0x04008010
+wm 32 MX6_MMDC_P0_MDSCR			0x04008040
+
+wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1390001
+check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1380000
+
+wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x001e001e
+wm 32 MX6_MMDC_P0_MPWLDECTRL1	0x001e001e
+wm 32 MX6_MMDC_P1_MPWLDECTRL0	0x001e001e
+wm 32 MX6_MMDC_P1_MPWLDECTRL1	0x001e001e
+
+wm 32 MX6_MMDC_P0_MDSCR			0x00048033
+wm 32 MX6_IOM_DRAM_SDQS0		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS1		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS2		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS3		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS4		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS5		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS6		0x00007030
+wm 32 MX6_IOM_DRAM_SDQS7		0x00007030
+
+wm 32 MX6_MMDC_P0_MDSCR			0x00008020
+wm 32 MX6_MMDC_P0_MDSCR			0x04008050
+
+wm 32 MX6_MMDC_P0_MPRDDLCTL		0x40404040
+wm 32 MX6_MMDC_P0_MPWRDLCTL		0x40404040
+wm 32 MX6_MMDC_P1_MPRDDLCTL		0x40404040
+wm 32 MX6_MMDC_P1_MPWRDLCTL		0x40404040
+wm 32 MX6_MMDC_P0_MPMUR0		0x00000800
+
+wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
+check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
+wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
+check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
+wm 32 MX6_MMDC_P0_MPDGCTRL0		0x50800000
+check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000
+
+wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS2		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS3		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS4		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS5		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS6		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS7		0x00000030
+
+wm 32 MX6_MMDC_P0_MDSCR			0x04008050
+wm 32 MX6_MMDC_P0_MPRDDLHWCTL		0x00000030
+wm 32 MX6_MMDC_P1_MPRDDLHWCTL		0x00000030
+
+check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+
+wm 32 MX6_MMDC_P0_MDSCR			0x04008050
+wm 32 MX6_MMDC_P0_MPWRDLHWCTL		0x00000030
+check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+
+wm 32 MX6_MMDC_P0_MDSCR			0x04008050
+wm 32 MX6_MMDC_P1_MPWRDLHWCTL		0x00000030
+check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+wm 32 MX6_MMDC_P0_MDSCR			0x00008033
+wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xa138002b
+wm 32 MX6_MMDC_P0_MDREF			0x00001800
+wm 32 MX6_MMDC_P0_MAPSR			0x00001006
+wm 32 MX6_MMDC_P0_MDPDC			0x0002556d
+wm 32 MX6_MMDC_P1_MDPDC			0x0002556d
+wm 32 MX6_MMDC_P0_MDSCR			0x00000000
+check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/Makefile b/arch/arm/boards/karo-tx6x/Makefile
new file mode 100644
index 0000000000..01c7a259e9
--- /dev/null
+++ b/arch/arm/boards/karo-tx6x/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/karo-tx6x/board.c b/arch/arm/boards/karo-tx6x/board.c
new file mode 100644
index 0000000000..6d9dd9a505
--- /dev/null
+++ b/arch/arm/boards/karo-tx6x/board.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2014 Steffen Trumtrar, Pengutronix
+ *
+ *
+ * with the PMIC init code taken from u-boot
+ * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <i2c/i2c.h>
+#include <linux/clk.h>
+#include <environment.h>
+#include <mach/bbu.h>
+#include <mach/imx6.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
+
+#define ETH_PHY_RST	IMX_GPIO_NR(7, 6)
+#define ETH_PHY_PWR	IMX_GPIO_NR(3, 20)
+#define ETH_PHY_INT	IMX_GPIO_NR(7, 1)
+#define DIV_ROUND_UP(n,d)      (((n) + (d) - 1) / (d))
+#define DIV_ROUND(n,d)         (((n) + ((d)/2)) / (d))
+
+#define LTC3676_BUCK1		0x01
+#define LTC3676_BUCK2		0x02
+#define LTC3676_BUCK3		0x03
+#define LTC3676_BUCK4		0x04
+#define LTC3676_DVB1A		0x0A
+#define LTC3676_DVB1B		0x0B
+#define LTC3676_DVB2A		0x0C
+#define LTC3676_DVB2B		0x0D
+#define LTC3676_DVB3A		0x0E
+#define LTC3676_DVB3B		0x0F
+#define LTC3676_DVB4A		0x10
+#define LTC3676_DVB4B		0x11
+#define LTC3676_MSKPG		0x13
+#define LTC3676_CLIRQ		0x1f
+
+#define LTC3676_BUCK_DVDT_FAST	(1 << 0)
+#define LTC3676_BUCK_KEEP_ALIVE	(1 << 1)
+#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
+#define LTC3676_BUCK_PHASE_SEL	(1 << 3)
+#define LTC3676_BUCK_ENABLE_300	(1 << 4)
+#define LTC3676_BUCK_PULSE_SKIP	(0 << 5)
+#define LTC3676_BUCK_BURST_MODE	(1 << 5)
+#define LTC3676_BUCK_CONTINUOUS	(2 << 5)
+#define LTC3676_BUCK_ENABLE	(1 << 7)
+
+#define LTC3676_PGOOD_MASK	(1 << 5)
+
+#define LTC3676_MSKPG_BUCK1	(1 << 0)
+#define LTC3676_MSKPG_BUCK2	(1 << 1)
+#define LTC3676_MSKPG_BUCK3	(1 << 2)
+#define LTC3676_MSKPG_BUCK4	(1 << 3)
+#define LTC3676_MSKPG_LDO2	(1 << 5)
+#define LTC3676_MSKPG_LDO3	(1 << 6)
+#define LTC3676_MSKPG_LDO4	(1 << 7)
+
+#define VDD_IO_VAL		mV_to_regval(vout_to_vref(3300 * 10, 5))
+#define VDD_IO_VAL_LP		mV_to_regval(vout_to_vref(3100 * 10, 5))
+#define VDD_IO_VAL_2		mV_to_regval(vout_to_vref(3300 * 10, 5_2))
+#define VDD_IO_VAL_2_LP		mV_to_regval(vout_to_vref(3100 * 10, 5_2))
+#define VDD_SOC_VAL		mV_to_regval(vout_to_vref(1425 * 10, 6))
+#define VDD_SOC_VAL_LP		mV_to_regval(vout_to_vref(900 * 10, 6))
+#define VDD_DDR_VAL		mV_to_regval(vout_to_vref(1500 * 10, 7))
+#define VDD_DDR_VAL_LP		mV_to_regval(vout_to_vref(1500 * 10, 7))
+#define VDD_CORE_VAL		mV_to_regval(vout_to_vref(1425 * 10, 8))
+#define VDD_CORE_VAL_LP		mV_to_regval(vout_to_vref(900 * 10, 8))
+
+/* LDO1 */
+#define R1_1			470
+#define R2_1			150
+/* LDO4 */
+#define R1_4			470
+#define R2_4			150
+/* Buck1 */
+#define R1_5			390
+#define R2_5			110
+#define R1_5_2			470
+#define R2_5_2			150
+/* Buck2 (SOC) */
+#define R1_6			150
+#define R2_6			180
+/* Buck3 (DDR) */
+#define R1_7			150
+#define R2_7			140
+/* Buck4 (CORE) */
+#define R1_8			150
+#define R2_8			180
+
+/* calculate voltages in 10mV */
+#define R1(idx)			R1_##idx
+#define R2(idx)			R2_##idx
+
+#define vout_to_vref(vout, idx)	((vout) * R2(idx) / (R1(idx) + R2(idx)))
+#define vref_to_vout(vref, idx)	DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
+
+#define mV_to_regval(mV)	DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
+#define regval_to_mV(v)		(((v) * 125 + 4125))
+
+static struct ltc3673_regs {
+	u8 addr;
+	u8 val;
+	u8 mask;
+} ltc3676_regs[] = {
+	{ LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
+	{ LTC3676_DVB2B, VDD_SOC_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+	{ LTC3676_DVB3B, VDD_DDR_VAL_LP, ~0x3f, },
+	{ LTC3676_DVB4B, VDD_CORE_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+	{ LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
+	{ LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
+	{ LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
+	{ LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
+	{ LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
+	{ LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
+	{ LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
+	{ LTC3676_CLIRQ, 0, }, /* clear interrupt status */
+};
+
+static struct ltc3673_regs ltc3676_regs_2[] = {
+	{ LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+	{ LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
+};
+
+
+static int setup_pmic_voltages(void)
+{
+	struct i2c_adapter *adapter = NULL;
+	struct i2c_client client;
+	int addr = 0x3c;
+	int bus = 0;
+	int i;
+	struct ltc3673_regs *r;
+
+	adapter = i2c_get_adapter(bus);
+	if (!adapter) {
+		pr_err("i2c bus %d not found\n", bus);
+		return -ENODEV;
+	}
+
+	client.adapter = adapter;
+	client.addr = addr;
+
+	r = ltc3676_regs;
+
+	for (i = 0; i < ARRAY_SIZE(ltc3676_regs); i++, r++) {
+		if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) {
+			pr_err("i2c write error\n");
+			return -EIO;
+		}
+	}
+
+	r = ltc3676_regs_2;
+
+	for (i = 0; i < ARRAY_SIZE(ltc3676_regs_2); i++, r++) {
+		if (i2c_write_reg(&client, r->addr, &r->val, 1) != 1) {
+			pr_err("i2c write error\n");
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+static void eth_init(void)
+{
+	void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
+	uint32_t val;
+
+	val = readl(iomux + IOMUXC_GPR1);
+	val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
+	writel(val, iomux + IOMUXC_GPR1);
+}
+
+static int tx6x_devices_init(void)
+{
+	if (!of_machine_is_compatible("karo,imx6dl-tx6dl") &&
+	    !of_machine_is_compatible("karo,imx6q-tx6q"))
+		return 0;
+
+	barebox_set_hostname("tx6u");
+
+	eth_init();
+
+	setup_pmic_voltages();
+
+	imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
+
+	return 0;
+}
+device_initcall(tx6x_devices_init);
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
new file mode 100644
index 0000000000..2a1c42aeed
--- /dev/null
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "1600mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c
new file mode 100644
index 0000000000..00008d403c
--- /dev/null
+++ b/arch/arm/boards/karo-tx6x/lowlevel.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2014 Steffen Trumtrar, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <image-metadata.h>
+#include <mach/generic.h>
+#include <sizes.h>
+
+static inline void setup_uart(void)
+{
+	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
+	void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR;
+	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
+
+	writel(0x1, iomuxbase + 0x0314);
+	writel(0x1, iomuxbase + 0x0318);
+	writel(0x1, iomuxbase + 0x0330);
+	writel(0x1, iomuxbase + 0x032c);
+
+	writel(0xffffffff, ccmbase + 0x68);
+	writel(0xffffffff, ccmbase + 0x6c);
+	writel(0xffffffff, ccmbase + 0x70);
+	writel(0xffffffff, ccmbase + 0x74);
+	writel(0xffffffff, ccmbase + 0x78);
+	writel(0xffffffff, ccmbase + 0x7c);
+	writel(0xffffffff, ccmbase + 0x80);
+
+	writel(0x00000000, uartbase + 0x80);
+	writel(0x00004027, uartbase + 0x84);
+	writel(0x00000784, uartbase + 0x88);
+	writel(0x00000a81, uartbase + 0x90);
+	writel(0x0000002b, uartbase + 0x9c);
+	writel(0x0001b0b0, uartbase + 0xb0);
+	writel(0x0000047f, uartbase + 0xa4);
+	writel(0x0000c34f, uartbase + 0xa8);
+	writel(0x00000001, uartbase + 0x80);
+
+	putc_ll('>');
+}
+
+extern char __dtb_imx6dl_tx6u_801x_start[];
+
+BAREBOX_IMD_TAG_STRING(tx6x_mx6_memsize_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0);
+
+ENTRY_FUNCTION(start_imx6dl_tx6x_1g, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	IMD_USED(tx6x_mx6_memsize_1G);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_imx6dl_tx6u_801x_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
diff --git a/arch/arm/boards/karo-tx6x/ram-base.imxcfg b/arch/arm/boards/karo-tx6x/ram-base.imxcfg
new file mode 100644
index 0000000000..e912fb0f2b
--- /dev/null
+++ b/arch/arm/boards/karo-tx6x/ram-base.imxcfg
@@ -0,0 +1,71 @@
+wm 32 MX6_IOM_DRAM_DQM0			0x00020030
+wm 32 MX6_IOM_DRAM_DQM1			0x00020030
+wm 32 MX6_IOM_DRAM_DQM2			0x00020030
+wm 32 MX6_IOM_DRAM_DQM3			0x00020030
+wm 32 MX6_IOM_DRAM_DQM4			0x00020030
+wm 32 MX6_IOM_DRAM_DQM5			0x00020030
+wm 32 MX6_IOM_DRAM_DQM6			0x00020030
+wm 32 MX6_IOM_DRAM_DQM7			0x00020030
+
+wm 32 MX6_IOM_DRAM_ADDR00		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR01		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR02		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR03		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR04		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR05		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR06		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR07		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR08		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR09		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR10		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR11		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR12		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR13		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR14		0x00000000
+wm 32 MX6_IOM_DRAM_ADDR15		0x00000000
+
+wm 32 MX6_IOM_DRAM_CAS			0x00020030
+wm 32 MX6_IOM_DRAM_RAS			0x00020030
+wm 32 MX6_IOM_DRAM_SDCLK_0		0x00020030
+wm 32 MX6_IOM_DRAM_SDCLK_1		0x00020030
+
+wm 32 MX6_IOM_DRAM_RESET		0x00020030
+wm 32 MX6_IOM_DRAM_SDCKE0		0x00003000
+wm 32 MX6_IOM_DRAM_SDCKE1		0x00003000
+wm 32 MX6_IOM_DRAM_SDBA0		0x00000000
+wm 32 MX6_IOM_DRAM_SDBA1		0x00000000
+wm 32 MX6_IOM_DRAM_SDBA2		0x00000000
+wm 32 MX6_IOM_DRAM_SDODT0		0x00003030
+wm 32 MX6_IOM_DRAM_SDODT1		0x00003030
+wm 32 MX6_IOM_GRP_B0DS			0x00000030
+wm 32 MX6_IOM_GRP_B1DS			0x00000030
+wm 32 MX6_IOM_GRP_B2DS			0x00000030
+wm 32 MX6_IOM_GRP_B3DS			0x00000030
+wm 32 MX6_IOM_GRP_B4DS			0x00000030
+wm 32 MX6_IOM_GRP_B5DS			0x00000030
+wm 32 MX6_IOM_GRP_B6DS			0x00000030
+wm 32 MX6_IOM_GRP_B7DS			0x00000030
+wm 32 MX6_IOM_GRP_ADDDS			0x00000030
+
+/* (differential input) */
+wm 32 MX6_IOM_DDRMODE_CTL		0x00020000
+/* disable ddr pullups */
+wm 32 MX6_IOM_GRP_DDRPKE		0x00000000
+/* (differential input) */
+wm 32 MX6_IOM_GRP_DDRMODE		0x00020000
+wm 32 MX6_IOM_GRP_CTLDS			0x00000030
+
+wm 32 MX6_IOM_GRP_DDR_TYPE		0x000c0000
+wm 32 MX6_IOM_GRP_DDRPKE		0x00002000
+/* GRP_DDRHYS */
+wm 32 MX6_IOM_GRP_DDRHYS		0x00000000
+
+/* Read data DQ Byte0-3 delay */
+wm 32 MX6_MMDC_P0_MPRDDQBY0DL		0x33333333
+wm 32 MX6_MMDC_P0_MPRDDQBY1DL		0x33333333
+wm 32 MX6_MMDC_P0_MPRDDQBY2DL		0x33333333
+wm 32 MX6_MMDC_P0_MPRDDQBY3DL		0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY0DL		0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY1DL		0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY2DL		0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY3DL		0x33333333