arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT

This patch is based on a patch from the U-Boot and fixes two errors with
the LCDC. Original commit message from Jyri Sarha [1]:
"Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock."

The register values are generated by testing, because there is no formula
to calculate them. Also from Jyri Sarha [1]:
"In practice the only rule to find an optimal value is to find as high as
possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO
underflows under worst case scenario. The worst case happens when the
highest pixel clock videomode with maximum bpp is used while memory
subsystem is stressed by endless stream of writes hitting the same
memory memory bank (can be the same address)."

It only contains the BeagleBone Black and the Phytec SoM, because I
don't have other boards.

[1] https://patchwork.ozlabs.org/patch/704013/

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index 100f64fdd9..a56b4b6240 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -41,6 +41,7 @@ static const struct am33xx_emif_regs ddr2_regs = {
 	.emif_tim1		= 0x0666B3C9,
 	.emif_tim2		= 0x243631CA,
 	.emif_tim3		= 0x0000033F,
+	.ocp_config		= 0x00141414,
 	.sdram_config		= 0x41805332,
 	.sdram_config2		= 0x41805332,
 	.sdram_ref_ctrl		= 0x0000081A,
@@ -97,6 +98,7 @@ static const struct am33xx_emif_regs ddr3_regs = {
 	.emif_tim1		= 0x0AAAD4DB,
 	.emif_tim2		= 0x266B7FDA,
 	.emif_tim3		= 0x501F867F,
+	.ocp_config		= 0x00141414,
 	.zq_config		= 0x50074BE4,
 	.sdram_config		= 0x61C05332,
 	.sdram_config2		= 0x0,
diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h
index 9576d265e5..4ea654db12 100644
--- a/arch/arm/boards/phytec-som-am335x/ram-timings.h
+++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h
@@ -45,6 +45,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAD4DB,
 			.emif_tim2		= 0x26437FDA,
 			.emif_tim3		= 0x501F83FF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C052B2,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,
@@ -66,6 +67,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAE4DB,
 			.emif_tim2		= 0x266B7FDA,
 			.emif_tim3		= 0x501F867F,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C05332,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,
@@ -87,6 +89,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAD4DB,
 			.emif_tim2		= 0x26437FDA,
 			.emif_tim3		= 0x501F83FF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C052B2,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,
@@ -106,6 +109,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAE4DB,
 			.emif_tim2		= 0x262F7FDA,
 			.emif_tim3		= 0x501F82BF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C05232,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,
@@ -125,6 +129,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAE4DB,
 			.emif_tim2		= 0x266B7FDA,
 			.emif_tim3		= 0x501F867F,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C05332,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30
@@ -144,6 +149,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAE4DB,
 			.emif_tim2		= 0x266B7FDA,
 			.emif_tim3		= 0x501F867F,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C053B2,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30
@@ -163,6 +169,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAE4DB,
 			.emif_tim2		= 0x268F7FDA,
 			.emif_tim3		= 0x501F88BF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C053B2,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30
@@ -182,6 +189,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1              = 0x0AAAD4DB,
 			.emif_tim2              = 0x26437FDA,
 			.emif_tim3              = 0x501F83FF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config           = 0x61C052B2,
 			.zq_config              = 0x50074BE4,
 			.sdram_ref_ctrl         = 0x00000C30,
@@ -203,6 +211,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAD4DB,
 			.emif_tim2		= 0x266B7FDA,
 			.emif_tim3		= 0x501F867F,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C05332,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,
@@ -222,6 +231,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAD4DB,
 			.emif_tim2		= 0x26437FDA,
 			.emif_tim3		= 0x501F83FF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C052B2,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,
@@ -241,6 +251,7 @@ struct am335x_sdram_timings physom_timings[] = {
 			.emif_tim1		= 0x0AAAD4DB,
 			.emif_tim2		= 0x268F7FDA,
 			.emif_tim3		= 0x501F88BF,
+			.ocp_config		= 0x003d3d3d,
 			.sdram_config		= 0x61C053B2,
 			.zq_config		= 0x50074BE4,
 			.sdram_ref_ctrl		= 0x00000C30,