ARM: add support for Nitrogen6MAX QP variant

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 98 insertions, 3 deletions

diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/1066mhz_4x512mx16-qp.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6x/1066mhz_4x512mx16-qp.imxcfg
new file mode 100644
index 0000000000..6409b745d7
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6x/1066mhz_4x512mx16-qp.imxcfg
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 Boundary Devices
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* NOC setup */
+wm 32 0x00bb0008				0x00000004
+wm 32 0x00bb000c				0x2891E41A
+wm 32 0x00bb0038				0x00000564
+wm 32 0x00bb0014				0x00000040
+wm 32 0x00bb0028				0x00000020
+wm 32 0x00bb002c				0x00000020
+
+/* Disable all MMDC arbitration and reordering controls */
+wm 32 0x021b0400				0x14420000
+
+wm 32 MX6_MMDC_P0_MDPDC			0x00020036
+wm 32 MX6_MMDC_P0_MDSCR			0x00008000
+wm 32 MX6_MMDC_P0_MDCFG0		0x898E79A4
+wm 32 MX6_MMDC_P0_MDCFG1		0xDB538F64
+wm 32 MX6_MMDC_P0_MDCFG2		0x01FF00DD
+wm 32 MX6_MMDC_P0_MDRWD			0x0f9f26d2
+wm 32 MX6_MMDC_P0_MDOR			0x008E1023
+wm 32 MX6_MMDC_P0_MDOTC			0x09444040
+wm 32 MX6_MMDC_P0_MDPDC			0x00025576
+wm 32 MX6_MMDC_P0_MDASP			0x00000047
+wm 32 MX6_MMDC_P0_MDCTL			0xC41A0000
+wm 32 MX6_MMDC_P0_MDSCR			0x04088032
+wm 32 MX6_MMDC_P0_MDSCR			0x0408803a
+wm 32 MX6_MMDC_P0_MDSCR			0x00008033
+wm 32 MX6_MMDC_P0_MDSCR			0x0000803b
+wm 32 MX6_MMDC_P0_MDSCR			0x00428031
+wm 32 MX6_MMDC_P0_MDSCR			0x00428039
+wm 32 MX6_MMDC_P0_MDSCR			0x19308030
+wm 32 MX6_MMDC_P0_MDSCR			0x19308038
+wm 32 MX6_MMDC_P0_MDSCR			0x04008040
+wm 32 MX6_MMDC_P0_MDSCR			0x04008048
+wm 32 MX6_MMDC_P0_MPZQHWCTRL	0xA1390003
+wm 32 MX6_MMDC_P1_MPZQHWCTRL	0xA1390003
+wm 32 MX6_MMDC_P0_MDREF			0x00007800
+wm 32 MX6_MMDC_P0_MPODTCTRL		0x00022227
+wm 32 MX6_MMDC_P1_MPODTCTRL		0x00022227
+wm 32 MX6_MMDC_P0_MPDGCTRL0		0x4327033b
+wm 32 MX6_MMDC_P0_MPDGCTRL1		0x0324031a
+wm 32 MX6_MMDC_P1_MPDGCTRL0		0x43240337
+wm 32 MX6_MMDC_P1_MPDGCTRL1		0x03210269
+wm 32 MX6_MMDC_P0_MPRDDLCTL		0x483c3e4a
+wm 32 MX6_MMDC_P1_MPRDDLCTL		0x423a3848
+wm 32 MX6_MMDC_P0_MPWRDLCTL		0x33363a2c
+wm 32 MX6_MMDC_P1_MPWRDLCTL		0x3e314137
+wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x00200026
+wm 32 MX6_MMDC_P0_MPWLDECTRL1	0x00260021
+wm 32 MX6_MMDC_P1_MPWLDECTRL0	0x00180028
+wm 32 MX6_MMDC_P1_MPWLDECTRL1	0x000f001e
+wm 32 MX6_MMDC_P0_MPMUR0		0x00000800
+wm 32 MX6_MMDC_P1_MPMUR0		0x00000800
+wm 32 MX6_MMDC_P0_MDSCR			0x00000000
+wm 32 MX6_MMDC_P0_MAPSR			0x00011006
diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/board.c b/arch/arm/boards/boundarydevices-nitrogen6x/board.c
index 28dba3af9a..d9514d9d48 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6x/board.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6x/board.c
@@ -23,13 +23,17 @@
 static int nitrogen6x_devices_init(void)
 {
 	if (!of_machine_is_compatible("boundary,imx6dl-nitrogen6x") &&
-	    !of_machine_is_compatible("boundary,imx6q-nitrogen6x"))
+	    !of_machine_is_compatible("boundary,imx6q-nitrogen6x") &&
+	    !of_machine_is_compatible("boundary,imx6qp-nitrogen6_max"))
 		return 0;
 
 	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
 			BBU_HANDLER_FLAG_DEFAULT);
 
-	barebox_set_hostname("nitrogen6x");
+	if (of_machine_is_compatible("boundary,imx6qp-nitrogen6_max"))
+		barebox_set_hostname("nitrogen6max");
+	else
+		barebox_set_hostname("nitrogen6x");
 
 	return 0;
 }
@@ -55,7 +59,8 @@ static int ksz9021rn_phy_fixup(struct phy_device *dev)
 static int nitrogen6x_coredevices_init(void)
 {
 	if (!of_machine_is_compatible("boundary,imx6dl-nitrogen6x") &&
-	    !of_machine_is_compatible("boundary,imx6q-nitrogen6x"))
+	    !of_machine_is_compatible("boundary,imx6q-nitrogen6x") &&
+	    !of_machine_is_compatible("boundary,imx6qp-nitrogen6_max"))
 		return 0;
 
 	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6qp-max.imxcfg
new file mode 100644
index 0000000000..66f0e1a860
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6qp-max.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "1066mhz_4x512mx16-qp.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
index 7eea3ce390..bee70a5af4 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
@@ -50,3 +50,16 @@ ENTRY_FUNCTION(start_imx6dl_nitrogen6x_2g, r0, r1, r2)
 
 	imx6q_barebox_entry(fdt);
 }
+
+extern char __dtb_imx6qp_nitrogen6_max_start[];
+
+ENTRY_FUNCTION(start_imx6qp_nitrogen6_max, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	fdt = __dtb_imx6qp_nitrogen6_max_start - get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}