diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-02-04 15:48:43 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-02-04 15:48:43 +0100 |
commit | 1b575024f67f43a3b325c1d3f021ac482b6fad81 (patch) | |
tree | fb36c110a86fd4d7517e107048b6c337aef7760d /arch/arm/boards | |
parent | ec2bfe6953c14a477eef546858ab139012c7c695 (diff) | |
parent | ab5418b570b24f5be1ac12c3804f6bf04ec48ad2 (diff) | |
download | barebox-1b575024f67f43a3b325c1d3f021ac482b6fad81.tar.gz barebox-1b575024f67f43a3b325c1d3f021ac482b6fad81.tar.xz |
Merge branch 'for-next/at91'
Conflicts:
arch/arm/boards/at91rm9200ek/init.c
arch/arm/boards/pm9263/init.c
arch/arm/configs/at91sam9n12ek_defconfig
arch/arm/mach-at91/Kconfig
Diffstat (limited to 'arch/arm/boards')
74 files changed, 3414 insertions, 440 deletions
diff --git a/arch/arm/boards/animeo_ip/Makefile b/arch/arm/boards/animeo_ip/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/animeo_ip/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/animeo_ip/config.h b/arch/arm/boards/animeo_ip/config.h new file mode 100644 index 0000000000..006820cf21 --- /dev/null +++ b/arch/arm/boards/animeo_ip/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/animeo_ip/env/config b/arch/arm/boards/animeo_ip/env/config new file mode 100644 index 0000000000..a0537b8829 --- /dev/null +++ b/arch/arm/boards/animeo_ip/env/config @@ -0,0 +1,39 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp-barebox +global.dhcp.vendor_id=barebox-animeo-ip + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=nfs +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net +# can be either 'nfs', 'tftp', 'nor', 'nand' or empty +oftree_loc=nfs + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +kernelimage=zImage +#kernelimage=uImage +#kernelimage=Image +#kernelimage=Image.lzo + +nand_device=atmel_nand +nand_parts="32k(at91bootstrap),256k(barebox)ro,32k(bareboxenv),704k(user_block),1728k(kernel),-(root)" +rootfs_mtdblock_nand=5 + +autoboot_timeout=3 + +bootargs="console=ttyS1,38400n8 earlyprintk" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c new file mode 100644 index 0000000000..ada3bb044e --- /dev/null +++ b/arch/arm/boards/animeo_ip/init.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Under GPLv2 only + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <fec.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <sizes.h> +#include <linux/mtd/nand.h> +#include <mach/board.h> +#include <mach/at91sam9_smc.h> +#include <gpio.h> +#include <mach/io.h> +#include <mach/at91_pmc.h> +#include <mach/at91_rstc.h> + +static bool animeo_ip_is_buco; +static bool animeo_ip_is_io; + +static int animeo_ip_get_pio_revision(int gpio, char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("animeo_ip: can not request gpio %d as %s (%d)\n", + gpio, name, ret); + return ret; + } + + ret = gpio_direction_input(gpio); + + if (ret) { + pr_err("animeo_ip: can configure gpio %d (%s) as input (%d)\n", + gpio, name, ret); + return ret; + } + + return gpio_get_value(gpio); +} + +static void animeo_ip_detect_version(void) +{ + struct device_d *dev = NULL; + char *model, *version; + int val; + + animeo_ip_is_io = false; + animeo_ip_is_buco = false; + model = "SubCo"; + version = "SDN"; + + dev = add_generic_device_res("animeo_ip", DEVICE_ID_SINGLE, NULL, 0, NULL); + + val = animeo_ip_get_pio_revision(AT91_PIN_PC20, "is_buco"); + if (val < 0) { + pr_warn("Can not detect model use %s by default\n", model); + } else if (val) { + animeo_ip_is_buco = true; + model = "SubCo"; + } + + val = animeo_ip_get_pio_revision(AT91_PIN_PC21, "is_io"); + if (val < 0) { + pr_warn("Can not detect version use %s by default\n", model); + } else if (val) { + animeo_ip_is_io = true; + version = "IO"; + } + + dev_add_param_fixed(dev, "model", model); + dev_add_param_fixed(dev, "version", version); +} + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .bus_width_16 = 0, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config animeo_ip_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void animeo_ip_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &animeo_ip_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .phy_addr = 0, +}; + +/* + * MCI (SD/MMC) + */ +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data __initdata animeo_ip_mci_data = { + .bus_width = 4, + .slot_b = 1, + .detect_pin = -EINVAL, + .wp_pin = -EINVAL, +}; + +static void animeo_ip_add_device_mci(void) +{ + at91_add_device_mci(0, &animeo_ip_mci_data); +} +#else +static void animeo_ip_add_device_mci(void) {} +#endif + +struct gpio_bicolor_led leds[] = { + { + .gpio_c0 = AT91_PIN_PC17, + .gpio_c1 = AT91_PIN_PA2, + .led = { + .name = "power_red_green", + }, + }, { + .gpio_c0 = AT91_PIN_PC19, + .gpio_c1 = AT91_PIN_PC18, + .led = { + .name = "tx_greem_rx_yellow", + }, + }, +}; + +static void __init animeo_ip_add_device_led(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(leds); i++) { + at91_set_gpio_output(leds[i].gpio_c0, leds[i].active_low); + at91_set_gpio_output(leds[i].gpio_c1, leds[i].active_low); + led_gpio_bicolor_register(&leds[i]); + } + led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); +} + +static int animeo_ip_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(animeo_ip_mem_init); + +static void animeo_export_gpio_in(int gpio, const char *name) +{ + at91_set_gpio_input(gpio, 0); + at91_set_deglitch(gpio, 1); + export_env_ull(name, gpio); +} + +static void animeo_ip_add_device_buttons(void) +{ + animeo_export_gpio_in(AT91_PIN_PB1, "keyswitch_in"); + animeo_export_gpio_in(AT91_PIN_PB2, "error_in"); + animeo_export_gpio_in(AT91_PIN_PC22, "jumper"); + animeo_export_gpio_in(AT91_PIN_PC23, "btn"); +} + +static void animeo_export_gpio_out(int gpio, const char *name) +{ + at91_set_gpio_output(gpio, 0); + export_env_ull(name, gpio); +} + +static void animeo_ip_power_control(void) +{ + animeo_export_gpio_out(AT91_PIN_PB0, "power_radio"); + animeo_export_gpio_out(AT91_PIN_PB3, "error_out_relay"); + animeo_export_gpio_out(AT91_PIN_PC4, "power_save"); +} + +static int animeo_ip_devices_init(void) +{ + animeo_ip_detect_version(); + animeo_ip_power_control(); + animeo_ip_add_device_nand(); + at91_add_device_eth(0, &macb_pdata); + animeo_ip_add_device_mci(); + animeo_ip_add_device_buttons(); + animeo_ip_add_device_led(); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + /* + * in production the machine id used is the cpu module machine id + * PICOCOM1 + */ + armlinux_set_architecture(MACH_TYPE_PICOCOM1); + + devfs_add_partition("nand0", 0x00000, SZ_32K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); + devfs_add_partition("nand0", SZ_32K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_256K + SZ_32K, SZ_32K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + return 0; +} + +device_initcall(animeo_ip_devices_init); + +static int animeo_ip_console_init(void) +{ + /* + * disable the dbgu enable by the bootstrap + * so linux can detect that we only enable the uart2 + * and use it for decompress + */ +#define ATMEL_US_BRGR 0x0020 + at91_sys_write(AT91_DBGU + ATMEL_US_BRGR, 0); + at91_register_uart(3, 0); + return 0; +} +console_initcall(animeo_ip_console_init); diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c index 0a360ae707..eec71bb07a 100644 --- a/arch/arm/boards/at91rm9200ek/init.c +++ b/arch/arm/boards/at91rm9200ek/init.c @@ -33,13 +33,13 @@ #include <spi/spi.h> static struct at91_ether_platform_data ether_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; static int at91rm9200ek_mem_init(void) { - at91_add_device_sdram(32 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c index 7bd02793b1..2d52f5a3f8 100644 --- a/arch/arm/boards/at91sam9260ek/init.c +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -127,7 +127,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile index eb072c0161..b6460c3982 100644 --- a/arch/arm/boards/at91sam9261ek/Makefile +++ b/arch/arm/boards/at91sam9261ek/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/at91sam9261ek/env/bin/init_board b/arch/arm/boards/at91sam9261ek/env/bin/init_board index a76a660aba..8e849c6a60 100644 --- a/arch/arm/boards/at91sam9261ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9261ek/env/bin/init_board @@ -1,5 +1,12 @@ #!/bin/sh +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + button_name="dfu_bp" button_wait=5 diff --git a/arch/arm/boards/at91sam9261ek/env/config b/arch/arm/boards/at91sam9261ek/env/config index 7d855779ca..cb3e847f54 100644 --- a/arch/arm/boards/at91sam9261ek/env/config +++ b/arch/arm/boards/at91sam9261ek/env/config @@ -34,8 +34,14 @@ kernelimage=zImage #kernelimage=Image.lzo nand_device=atmel_nand -nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" -rootfs_mtdblock_nand=6 +if [ x$borebox_first_stage = x1 ] +then + nand_parts="384k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" + rootfs_mtdblock_nand=5 +else + nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" + rootfs_mtdblock_nand=6 +fi autoboot_timeout=3 diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index 7c95435c8d..177bb34273 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -30,13 +30,14 @@ #include <linux/mtd/nand.h> #include <mach/at91_pmc.h> #include <mach/board.h> -#include <mach/gpio.h> +#include <gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> #include <dm9000.h> #include <gpio_keys.h> #include <readkey.h> #include <led.h> +#include <spi/spi.h> static struct atmel_nand_data nand_pdata = { .ale = 22, @@ -149,6 +150,86 @@ static void ek_add_device_udc(void) static void ek_add_device_udc(void) {} #endif +/* + * LCD Controller + */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + +/* TFT */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9261_DEFAULT_TFT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_tft_power_control(int on) +{ + if (on) + gpio_set_value(AT91_PIN_PA12, 0); /* power up */ + else + gpio_set_value(AT91_PIN_PA12, 1); /* power down */ +} + +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2, + .guard_time = 1, + .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static int at91_lcdc_gpio(void) +{ + return ek_gpio_request_output(AT91_PIN_PA12, "lcdc_tft_power"); +} + +static void ek_add_device_lcdc(void) +{ + if (at91_lcdc_gpio()) + return; + + if (machine_is_at91sam9g10ek()) + ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB; + + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + #ifdef CONFIG_KEYBOARD_GPIO struct gpio_keys_button keys[] = { { @@ -229,6 +310,46 @@ static void ek_device_add_leds(void) static void ek_device_add_leds(void) {} #endif +/* + * SPI related devices + */ +#if defined(CONFIG_DRIVER_SPI_ATMEL) +/* + * SPI devices + */ +static struct spi_board_info ek_spi_devices[] = { + { /* DataFlash chip */ + .name = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */ + .name = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PA3, AT91_PIN_PA6}; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, + ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} +#else +static void ek_add_device_spi(void) {} +#endif + static int at91sam9261ek_mem_init(void) { at91_add_device_sdram(0); @@ -239,15 +360,28 @@ mem_initcall(at91sam9261ek_mem_init); static int at91sam9261ek_devices_init(void) { + u32 barebox_part_start; + u32 barebox_part_size; ek_add_device_nand(); ek_add_device_dm9000(); ek_add_device_udc(); ek_add_device_buttons(); ek_device_add_leds(); - - devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); - devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); + ek_add_device_lcdc(); + ek_add_device_spi(); + + if (IS_ENABLED(CONFIG_AT91_LOAD_BAREBOX_SRAM)) { + barebox_part_start = 0; + barebox_part_size = SZ_256K + SZ_128K; + export_env_ull("borebox_first_stage", 1); + } else { + devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + barebox_part_start = SZ_128K; + barebox_part_size = SZ_256K; + } + devfs_add_partition("nand0", barebox_part_start, barebox_part_size, + DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c new file mode 100644 index 0000000000..056584166c --- /dev/null +++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_CLOCK 200 + +#if MASTER_CLOCK == 200 +#define MASTER_PLL_MUL 162 +#define MASTER_PLL_DIV 15 +#elif MASTER_CLOCK == 239 +#define MASTER_PLL_MUL 13 +#define MASTER_PLL_DIV 1 +#endif + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC; + + cfg->smc_cs = 3; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_8 | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_TDF_(2); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3); + cfg->smc_setup = + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (8 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = (MASTER_CLOCK * 7); + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile index eb072c0161..b6460c3982 100644 --- a/arch/arm/boards/at91sam9263ek/Makefile +++ b/arch/arm/boards/at91sam9263ek/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/at91sam9263ek/config.h b/arch/arm/boards/at91sam9263ek/config.h index 14eb4fe241..cc12040e80 100644 --- a/arch/arm/boards/at91sam9263ek/config.h +++ b/arch/arm/boards/at91sam9263ek/config.h @@ -3,91 +3,4 @@ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define MASTER_PLL_MUL 171 -#define MASTER_PLL_DIV 14 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (1 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC_CS 0 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9263ek/env/bin/init_board b/arch/arm/boards/at91sam9263ek/env/bin/init_board index ae2ac7d766..f2e6294648 100644 --- a/arch/arm/boards/at91sam9263ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9263ek/env/bin/init_board @@ -1,5 +1,12 @@ #!/bin/sh +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + button_name="dfu_bp" button_wait=5 diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index a86c0fd510..90fdbeca76 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -32,7 +32,7 @@ #include <linux/mtd/nand.h> #include <mach/at91_pmc.h> #include <mach/board.h> -#include <mach/gpio.h> +#include <gpio.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> @@ -83,7 +83,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -149,6 +149,75 @@ static void ek_add_device_udc(void) static void ek_add_device_udc(void) {} #endif +/* + * LCD Controller + */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "TX09D50VM1CCA @ 60", + .refresh = 60, + .xres = 240, .yres = 320, + .pixclock = KHZ2PICOS(4965), + + .left_margin = 1, .right_margin = 33, + .upper_margin = 1, .lower_margin = 0, + .hsync_len = 5, .vsync_len = 1, + + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + gpio_set_value(AT91_PIN_PA30, on); +} + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2, + .guard_time = 1, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + if (ek_gpio_request_output(AT91_PIN_PA30, "lcdc_power")) + return; + + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + static void __init ek_add_device_buttons(void) { at91_set_gpio_input(AT91_PIN_PC5, 1); @@ -184,6 +253,7 @@ static int at91sam9263ek_devices_init(void) ek_device_add_leds(); ek_add_device_udc(); ek_add_device_buttons(); + ek_add_device_lcdc(); if (IS_ENABLED(CONFIG_DRIVER_CFI) && cdev_by_name("nor0")) { devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self"); diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c new file mode 100644 index 0000000000..2f8b312d34 --- /dev/null +++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_PLL_MUL 171 +#define MASTER_PLL_DIV 14 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 0; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (2 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_DBW_32 | + (1 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (1 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 1200; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board index 3d7426f527..73daecc001 100644 --- a/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board +++ b/arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board @@ -5,6 +5,13 @@ export PATH . /env/config +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + menu -r -m boot menu -a -m boot -d "\e[1;36mWelcome on Barebox Boot Sequence\e[0m" menu -e -a -m boot -c 'menu_boot' -d "boot (default) " diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c index 053c85b433..5b5e31b554 100644 --- a/arch/arm/boards/at91sam9m10g45ek/init.c +++ b/arch/arm/boards/at91sam9m10g45ek/init.c @@ -106,7 +106,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -208,21 +208,84 @@ static void ek_device_add_keyboard(void) static void ek_device_add_keyboard(void) {} #endif +#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) +/* + * USB HS Host port (common to OHCI & EHCI) + */ +static struct at91_usbh_data ek_usbh_hs_data = { + .ports = 2, + .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3}, + .vbus_pin_active_low = {1, 1}, +}; + +static void ek_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); + at91_add_device_usbh_ehci(&ek_usbh_hs_data); +} +#else +static void ek_add_device_usb(void) {} +#endif + static int at91sam9m10g45ek_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } mem_initcall(at91sam9m10g45ek_mem_init); +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 480, .yres = 272, + .pixclock = KHZ2PICOS(9000), + + .left_margin = 1, .right_margin = 1, + .upper_margin = 40, .lower_margin = 1, + .hsync_len = 45, .vsync_len = 1, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 32, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + + static int at91sam9m10g45ek_devices_init(void) { ek_add_device_nand(); at91_add_device_eth(0, &macb_pdata); ek_add_device_mci(); + ek_add_device_usb(); ek_device_add_leds(); ek_device_add_keyboard(); + ek_add_device_lcdc(); devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); diff --git a/arch/arm/boards/at91sam9m10ihd/Makefile b/arch/arm/boards/at91sam9m10ihd/Makefile new file mode 100644 index 0000000000..f2acf201b4 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/Makefile @@ -0,0 +1,2 @@ +obj-y += init.o +obj-y += hw_version.o diff --git a/arch/arm/boards/at91sam9m10ihd/config.h b/arch/arm/boards/at91sam9m10ihd/config.h new file mode 100644 index 0000000000..ac3114d865 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/android b/arch/arm/boards/at91sam9m10ihd/env/boot/android new file mode 100644 index 0000000000..e440f18068 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/android @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "android (nand)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +global.linux.bootargs.dyn.root="root=/dev/mtdblock1 rootfstype=jffs2 rw init=/init rootdelay=1" +# clean the mtdparts otherwise android does not boot +global -r linux.mtdparts. diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/mmc b/arch/arm/boards/at91sam9m10ihd/env/boot/mmc new file mode 100644 index 0000000000..89c66ee8fc --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/mmc @@ -0,0 +1,19 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "MMC slot" + exit +fi + +path="/mnt/mmc" + +global.bootm.image="${path}/zimage" + +oftree=${path}/oftree +if [ -f $oftree ]; then + global.bootm.oftree="$oftree" +fi + +# The rootdevice may actually be mmcblk1p2 if a card +# is inserted to the back MMC slot +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2" diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/net b/arch/arm/boards/at91sam9m10ihd/env/boot/net new file mode 100644 index 0000000000..cdb2520d39 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/net @@ -0,0 +1,16 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "network (tftp, nfs) (macb)" + exit +fi + +ethact eth0 + +path="/mnt/tftp" + +global.bootm.image="${path}/${global.user}-linux-${global.hostname}" +#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}" +nfsroot="/home/${global.user}/nfsroot/${global.hostname}" +bootargs-ip +global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" diff --git a/arch/arm/boards/at91sam9m10ihd/env/boot/net-usb b/arch/arm/boards/at91sam9m10ihd/env/boot/net-usb new file mode 100644 index 0000000000..6e341a0114 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/boot/net-usb @@ -0,0 +1,22 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "network (tftp, nfs) (usb ethernet)" + exit +fi + +usb -f +ethact eth1 + +if [ $? -ne 0 ]; then + echo "ERROR: usb ethernet not found" + exit 1 +fi + +path="/mnt/tftp" + +global.bootm.image="${path}/${global.user}-linux-${global.hostname}" +#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}" +nfsroot="/home/${global.user}/nfsroot/${global.hostname}" +bootargs-ip +global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" diff --git a/arch/arm/boards/at91sam9m10ihd/env/config b/arch/arm/boards/at91sam9m10ihd/env/config new file mode 100644 index 0000000000..bc2119ee96 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/config @@ -0,0 +1,21 @@ +#!/bin/sh + +# change network settings in /env/network/eth0 +# change mtd partition settings and automountpoints in /env/init/* + +#global.hostname= + +# set to false if you do not want to have colors +global.allow_color=true + +# user (used for network filenames) +global.user=none + +# timeout in seconds before the default boot entry is started +global.autoboot_timeout=3 + +# default boot entry (one of /env/boot/*) +global.boot.default=android + +# base bootargs +#global.linux.bootargs.base="console=ttyS0,115200" diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/automount b/arch/arm/boards/at91sam9m10ihd/env/init/automount new file mode 100644 index 0000000000..5bb63ccb9e --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/automount @@ -0,0 +1,17 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +# automount nfs server example + +# SD card slot, first partition +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mount /dev/disk0.0 /mnt/mmc' diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/config-board b/arch/arm/boards/at91sam9m10ihd/env/init/config-board new file mode 100644 index 0000000000..32c107130b --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/config-board @@ -0,0 +1,8 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=at91sam9m10ihd +global.linux.bootargs.base="console=ttyS0,115200" +global.boot.default=android diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand new file mode 100644 index 0000000000..ac516d82d7 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="128k(nand0.at91bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.bareboxenv2),128k(nand0.oftree),1280k(nand0.free),3M(nand0.kernel),195M(nand0.rootfs),300M(nand0.userdata),-(nand0.cache)" +kernelname="atmel_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 new file mode 100644 index 0000000000..44198c820e --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "SPI NOR partitions" + exit +fi + +mtdparts="32k(m25p0.at91bootstrap)ro,256k(m25p0.barebox),128k(m25p0.bareboxenv),128k(m25p0.bareboxenv2),128k(m25p0.oftree),-(m25p0.kernel)" +kernelname="m25p0" + +mtdparts-add -d m25p0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/ps1 b/arch/arm/boards/at91sam9m10ihd/env/init/ps1 new file mode 100644 index 0000000000..a94acc14f8 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/ps1 @@ -0,0 +1,9 @@ +#!/bin/sh + +/env/config + +if [ ${global.allow_color} = "true" ]; then + export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# " +else + export PS1="barebox@\h:\w\n# " +fi diff --git a/arch/arm/boards/at91sam9m10ihd/env/init/splash b/arch/arm/boards/at91sam9m10ihd/env/init/splash new file mode 100644 index 0000000000..18e74dfcc9 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/env/init/splash @@ -0,0 +1,8 @@ +#!/bin/sh + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c new file mode 100644 index 0000000000..cd522f7b2c --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include <common.h> +#include <fs.h> +#include <fcntl.h> +#include <libbb.h> +#include <asm/armlinux.h> +#include <of.h> +#include <libfdt.h> + +#include "hw_version.h" + +enum board_type { + BOARD_TYPE_DB, + BOARD_TYPE_CPU, +}; + +static struct board_info { + char *name; + enum board_type type; + unsigned char id; +} board_list[] = { + {"SAM9M10-CM", BOARD_TYPE_CPU, 0}, + {"IHD-DB-9M10", BOARD_TYPE_DB, 1}, +}; + +static struct board_info* get_board_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(board_list); i++) + if (strcmp(name, board_list[i].name) == 0) + return &board_list[i]; + + return NULL; +} + +static struct vendor_info { + char *name; + enum vendor_id id; +} vendor_list[] = { + {"ATMEL_SH", VENDOR_ATMEL}, + {"FLEX", VENDOR_FLEX}, +}; + +static struct vendor_info* get_vendor_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vendor_list); i++) + if (strcmp(name, vendor_list[i].name) == 0) + return &vendor_list[i]; + + return NULL; +} + +#define BOARD_NAME_LEN 12 +#define VENDOR_NAME_LEN 10 +#define VENDOR_COUNTRY_LEN 2 + +struct one_wire_info { + u8 total_bytes; + u8 vendor_name[VENDOR_NAME_LEN]; + u8 vendor_country[VENDOR_COUNTRY_LEN]; + u8 board_name[BOARD_NAME_LEN]; + u8 year; + u8 week; + u8 revision_code; + u8 revision_id; + u8 reserved; + u8 checksum_l; + u8 checksum_h; +}__attribute__ ((packed)); + +static int at91sam9m10ihd_read_w1(const char *file, struct one_wire_info *info) +{ + int fd; + int ret; + + fd = open(file, O_RDONLY); + if (fd < 0) { + ret = fd; + goto err; + } + + ret = read_full(fd, info, sizeof(*info)); + if (ret < 0) + goto err_open; + + if (ret < sizeof(*info)) { + ret = -EINVAL; + goto err_open; + } + + pr_debug("total_bytes = %d\n", info->total_bytes); + pr_debug("vendor_name = %s\n", info->vendor_name); + pr_debug("vendor_country = %.2s\n", info->vendor_country); + pr_debug("board_name = %s\n", info->board_name); + pr_debug("year = %d\n", info->year); + pr_debug("week = %d\n", info->week); + pr_debug("revision_code = %x\n", info->revision_code); + pr_debug("revision_id = %x\n", info->revision_id); + pr_debug("reserved = %x\n", info->reserved); + pr_debug("checksum_l = %x\n", info->checksum_l); + pr_debug("checksum_h = %x\n", info->checksum_h); + + ret = 0; + +err_open: + close(fd); +err: + if (ret) + pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret)); + return ret; +} + +static u32 sn = 0; +static u32 rev = 0; + +bool at91sam9m10ihd_cm_is_vendor(enum vendor_id vid) +{ + return ((sn >> 5) & 0x1f) == vid; +} + +bool at91sam9m10ihd_db_is_vendor(enum vendor_id vid) +{ + return ((sn >> 15) & 0x1f) == vid; +} + +static void at91sam9m10ihd_devices_detect_one(const char *name) +{ + struct one_wire_info info; + struct board_info* binfo; + struct vendor_info* vinfo; + struct device_d *dev = NULL; + char str[16]; + u8 vendor_id = 0; + + if (at91sam9m10ihd_read_w1(name, &info)) + return; + + binfo = get_board_info_by_name(info.board_name); + + if (!binfo) { + pr_err("board %s no supported\n", info.board_name); + return; + } + + vinfo = get_vendor_info_by_name(info.vendor_name); + if (vinfo) + vendor_id = vinfo->id; + + switch (binfo->type) { + case BOARD_TYPE_CPU: + dev = add_generic_device_res("at91sam9m10ihd", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= (binfo->id & 0x1f); + sn |= ((vendor_id & 0x1f) << 5); + rev |= (info.revision_code - 'A'); + rev |= (((info.revision_id - '0') & 0x3) << 15); + pr_info("CM"); + break; + case BOARD_TYPE_DB: + dev = add_generic_device_res("at91sam9m10ihd-db", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= ((binfo->id & 0x1f) << 20); + sn |= ((vendor_id & 0x1f) << 25); + rev |= ((info.revision_code - 'A') << 10); + rev |= (((info.revision_id - '0') & 0x3) << 21); + pr_info("DB"); + break; + } + + pr_info(": %s [%c%c] from %s\n", + info.board_name, info.revision_code, info.revision_id, + info.vendor_name); + + dev_add_param_fixed(dev, "vendor", info.vendor_name); + dev_add_param_fixed(dev, "board", info.board_name); + sprintf(str, "%.2s", info.vendor_country); + dev_add_param_fixed(dev, "country", str); + sprintf(str, "%d", info.year); + dev_add_param_fixed(dev, "year", str); + sprintf(str, "%d", info.week); + dev_add_param_fixed(dev, "week", str); + sprintf(str, "%c", info.revision_code); + dev_add_param_fixed(dev, "revision_code", str); + sprintf(str, "%c", info.revision_id); + dev_add_param_fixed(dev, "revision_id", str); +} + +void at91sam9m10ihd_devices_detect_hw(void) +{ + at91sam9m10ihd_devices_detect_one("/dev/ds24310"); + at91sam9m10ihd_devices_detect_one("/dev/ds24330"); + + pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); + armlinux_set_revision(rev); + armlinux_set_serial(sn); +} diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.h b/arch/arm/boards/at91sam9m10ihd/hw_version.h new file mode 100644 index 0000000000..b9133440d3 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HW_REVISION_H__ +#define __HW_REVISION_H__ + +enum vendor_id { + VENDOR_UNKNOWN = 0, + VENDOR_ATMEL = 1, + VENDOR_FLEX = 2, +}; + +void at91sam9m10ihd_devices_detect_hw(void); + +bool at91sam9m10ihd_cm_is_vendor(enum vendor_id vid); +bool at91sam9m10ihd_db_is_vendor(enum vendor_id vid); + +#endif /* __HW_REVISION_H__ */ diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c new file mode 100644 index 0000000000..f258caf2b4 --- /dev/null +++ b/arch/arm/boards/at91sam9m10ihd/init.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Under GPLv2 only + */ + +#include <common.h> +#include <net.h> +#include <mci.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <sizes.h> +#include <linux/mtd/nand.h> +#include <mach/board.h> +#include <gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <input/qt1070.h> +#include <readkey.h> +#include <linux/w1-gpio.h> +#include <w1_mac_address.h> +#include <spi/spi.h> + +#include "hw_version.h" + +struct w1_gpio_platform_data w1_pdata = { + .pin = AT91_PIN_PB25, + .ext_pullup_enable_pin = -EINVAL, + .is_open_drain = 0, +}; + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC15, + .enable_pin = AT91_PIN_PC14, + .bus_width_16 = 0, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, +}; + +static void ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &ek_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static void ek_add_device_eth(void) +{ + if (w1_local_mac_address_register(0, "tml", "w1-2d-0")) + w1_local_mac_address_register(0, "tml", "w1-23-0"); + + at91_add_device_eth(0, &macb_pdata); +} + +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data ek_mci0_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PC25, +}; + +static void ek_add_device_mci(void) +{ + at91_add_device_mci(0, &ek_mci0_data); +} +#else +static void ek_add_device_mci(void) {} +#endif + +struct qt1070_platform_data qt1070_pdata = { + .irq_pin = AT91_PIN_PB19, + .code = { KEY_ENTER, KEY_ENTER, KEY_UP, KEY_DOWN, }, + .nb_code = 4, +}; + +static struct i2c_board_info i2c_devices[] = { + { + .platform_data = &qt1070_pdata, + I2C_BOARD_INFO("qt1070", 0x1b), + }, { + I2C_BOARD_INFO("24c512", 0x51) + }, +}; + +static void ek_add_device_i2c(void) +{ + at91_set_gpio_input(qt1070_pdata.irq_pin, 0); + at91_set_deglitch(qt1070_pdata.irq_pin, 1); + at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices)); +} + +static const struct spi_board_info ek_spi_devices[] = { + { + .name = "m25p80", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + } +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PB3 }; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, + ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} + +/* + * USB HS Host port (common to OHCI & EHCI) + */ +static struct at91_usbh_data ek_usbh_hs_data = { + .ports = 1, + .vbus_pin = {AT91_PIN_PC30, -EINVAL}, + .vbus_pin_active_low = {1, 0}, +}; + +static void ek_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); + at91_add_device_usbh_ehci(&ek_usbh_hs_data); +} + +static int at91sam9m10g45ek_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(at91sam9m10g45ek_mem_init); + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + +static struct fb_videomode at91fb_default_monspecs[] = { + { + .name = "MULTEK", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(15000), + + .left_margin = 40, .right_margin = 40, + .upper_margin = 29, .lower_margin = 13, + .hsync_len = 48, .vsync_len = 3, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ + | ATMEL_LCDC_DISTYPE_TFT \ + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) + +static void at91_lcdc_power_control(int on) +{ + gpio_set_value(AT91_PIN_PE6, on); +} + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .mode_list = at91fb_default_monspecs, + .num_modes = ARRAY_SIZE(at91fb_default_monspecs), +}; + +static void ek_add_device_lcd(void) +{ + if (ek_gpio_request_output(AT91_PIN_PE6, "lcdc_power")) + return; + + at91_add_device_lcdc(&ek_lcdc_data); +} +#else +static void ek_add_device_lcd(void) {} +#endif + +static void ek_add_device_w1(void) +{ + at91_set_gpio_input(w1_pdata.pin, 0); + at91_set_multi_drive(w1_pdata.pin, 1); + add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); + + at91sam9m10ihd_devices_detect_hw(); +} + +static int at91sam9m10ihd_devices_init(void) +{ + ek_add_device_w1(); + ek_add_device_nand(); + ek_add_device_eth(); + ek_add_device_mci(); + ek_add_device_spi(); + ek_add_device_i2c(); + ek_add_device_usb(); + ek_add_device_lcd(); + + devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); + devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1"); + dev_add_bb_dev("env_raw1", "env1"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100)); + /* + * The internal Atmel kernel use the SAM9M10G45EK machine id + * The mainline use DT + */ + armlinux_set_architecture(MACH_TYPE_AT91SAM9M10G45EK); + + return 0; +} +device_initcall(at91sam9m10ihd_devices_init); + +static int at91sam9m10ihd_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(at91sam9m10ihd_console_init); diff --git a/arch/arm/boards/at91sam9n12ek/env/bin/init_board b/arch/arm/boards/at91sam9n12ek/env/bin/init_board index 977430debd..b41b63847d 100644 --- a/arch/arm/boards/at91sam9n12ek/env/bin/init_board +++ b/arch/arm/boards/at91sam9n12ek/env/bin/init_board @@ -1,5 +1,12 @@ #!/bin/sh +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + button_name="dfu_bp" button_wait=5 diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index 2fe7a1142e..a1816664f1 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -124,6 +124,75 @@ static void __init ek_add_device_ks8851(void) static void __init ek_add_device_ks8851(void) {} #endif /* CONFIG_DRIVER_NET_KS8851_MLL */ +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +static int ek_gpio_request_output(int gpio, const char *name) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) { + pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret) + pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret); + return ret; +} + + +/* + * LCD Controller + */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "QD", + .refresh = 60, + .xres = 480, .yres = 272, + .pixclock = KHZ2PICOS(9000), + + .left_margin = 8, .right_margin = 43, + .upper_margin = 4, .lower_margin = 12, + .hsync_len = 5, .vsync_len = 10, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Default output mode is TFT 24 bit */ +#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) + +static void at91_lcdc_power_control(int on) +{ + gpio_set_value(AT91_PIN_PC25, !on); +} + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .atmel_lcdfb_power_control = at91_lcdc_power_control, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + if (ek_gpio_request_output(AT91_PIN_PC25, "lcdc_power")) + return; + + at91_add_device_lcdc(&ek_lcdc_data); +} +#else +static void ek_add_device_lcdc(void) {} +#endif + /* * MCI (SD/MMC) */ @@ -228,7 +297,7 @@ static void __init ek_add_device_buttons(void) static int at91sam9n12ek_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } @@ -244,6 +313,7 @@ static int at91sam9n12ek_devices_init(void) ek_add_device_i2c(); ek_add_device_ks8851(); ek_add_device_buttons(); + ek_add_device_lcdc(); armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); armlinux_set_architecture(CONFIG_MACH_AT91SAM9N12EK); diff --git a/arch/arm/boards/at91sam9x5ek/env/bin/init_board b/arch/arm/boards/at91sam9x5ek/env/bin/init_board new file mode 100644 index 0000000000..f3d417e356 --- /dev/null +++ b/arch/arm/boards/at91sam9x5ek/env/bin/init_board @@ -0,0 +1,15 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + +exit 1 diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c index bcb961a948..4e1e069564 100644 --- a/arch/arm/boards/at91sam9x5ek/init.c +++ b/arch/arm/boards/at91sam9x5ek/init.c @@ -106,7 +106,7 @@ static void ek_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -118,6 +118,49 @@ static void ek_add_device_eth(void) at91_add_device_eth(0, &macb_pdata); } +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +/* + * LCD Controller + */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(33260), + + .left_margin = 88, .right_margin = 168, + .upper_margin = 8, .lower_margin = 37, + .hsync_len = 128, .vsync_len = 2, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Default output mode is TFT 24 bit */ +#define AT91SAM9X5_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_lcdcon2 = AT91SAM9X5_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + /* * MCI (SD/MMC) */ @@ -192,14 +235,24 @@ static void ek_add_device_spi(void) at91_add_device_spi(0, &spi_pdata); } +#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) /* - * USB Host port + * USB HS Host port (common to OHCI & EHCI) */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, - .vbus_pin = {AT91_PIN_PD20, AT91_PIN_PD19}, +static struct at91_usbh_data ek_usbh_hs_data = { + .ports = 2, + .vbus_pin = {AT91_PIN_PD19, AT91_PIN_PD20}, }; +static void ek_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_hs_data); + at91_add_device_usbh_ehci(&ek_usbh_hs_data); +} +#else +static void ek_add_device_usb(void) {} +#endif + struct gpio_led leds[] = { { .gpio = AT91_PIN_PB18, @@ -228,7 +281,7 @@ static void __init ek_add_led(void) static int at91sam9x5ek_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } @@ -250,9 +303,10 @@ static int at91sam9x5ek_devices_init(void) ek_add_device_eth(); ek_add_device_spi(); ek_add_device_mci(); - at91_add_device_usbh_ohci(&ek_usbh_data); + ek_add_device_usb(); ek_add_led(); ek_add_device_i2c(); + ek_add_device_lcdc(); armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); armlinux_set_architecture(CONFIG_MACH_AT91SAM9X5EK); diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c index f9ac7a469f..86de3b0f17 100644 --- a/arch/arm/boards/beaglebone/board.c +++ b/arch/arm/boards/beaglebone/board.c @@ -27,7 +27,7 @@ #include <driver.h> #include <fs.h> #include <linux/stat.h> -#include <environment.h> +#include <envfs.h> #include <sizes.h> #include <io.h> #include <ns16550.h> diff --git a/arch/arm/boards/mmccpu/Makefile b/arch/arm/boards/mmccpu/Makefile index eb072c0161..b6460c3982 100644 --- a/arch/arm/boards/mmccpu/Makefile +++ b/arch/arm/boards/mmccpu/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/mmccpu/config.h b/arch/arm/boards/mmccpu/config.h index e6215dc460..c896a93b40 100644 --- a/arch/arm/boards/mmccpu/config.h +++ b/arch/arm/boards/mmccpu/config.h @@ -3,122 +3,4 @@ #define AT91_MAIN_CLOCK 18432000 -/* values */ -#define MASTER_PLL_MUL 54 -#define MASTER_PLL_DIV 4 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13c -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* tWR - Write Recovery Delay */ \ - (8 << 12) | /* tRC - Row Cycle Delay */ \ - (2 << 16) | /* tRP - Row Precharge Delay */ \ - (2 << 20) | /* tRCD - Row to Column Delay */ \ - (5 << 24) | /* tRAS - Active to Precharge Delay */ \ - (12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */ - -/* setup CS0 (NOR Flash) - 16-bit */ -#define CONFIG_SYS_SMC_CS 0 -#if 1 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ - AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) -#elif 0 /* slow setup */ -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \ - AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \ - AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(1)) -#else /* RONETIX' original values */ -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) -#endif - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/mmccpu/lowlevel_init.c b/arch/arm/boards/mmccpu/lowlevel_init.c new file mode 100644 index 0000000000..c193eae58e --- /dev/null +++ b/arch/arm/boards/mmccpu/lowlevel_init.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_PLL_MUL 54 +#define MASTER_PLL_DIV 4 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | + AT91_MATRIX_EBI0_CS1A_SDRAMC | + AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA; + + cfg->smc_cs = 0; +#if 1 + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13); + cfg->smc_setup = + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0); +#elif 0 /* slow setup */ + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(1); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | + AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13); + cfg->smc_setup = + AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0); +#else /* RONETIX' original values */ + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); +#endif + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (2 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* tWR - Write Recovery Delay */ + (8 << 12) | /* tRC - Row Cycle Delay */ + (2 << 16) | /* tRP - Row Precharge Delay */ + (2 << 20) | /* tRCD - Row to Column Delay */ + (5 << 24) | /* tRAS - Active to Precharge Delay */ + (12 << 28); /* tXSR - Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 780; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c index c5d8fe6409..f1fbd5e944 100644 --- a/arch/arm/boards/panda/board.c +++ b/arch/arm/boards/panda/board.c @@ -19,7 +19,7 @@ #include <sizes.h> #include <asm/mmu.h> #include <mach/gpio.h> -#include <environment.h> +#include <envfs.h> #include <mach/xload.h> #include <i2c/i2c.h> #include <gpio.h> diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile index eb072c0161..b6460c3982 100644 --- a/arch/arm/boards/pm9261/Makefile +++ b/arch/arm/boards/pm9261/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h index 4602aa7e83..006820cf21 100644 --- a/arch/arm/boards/pm9261/config.h +++ b/arch/arm/boards/pm9261/config.h @@ -3,91 +3,4 @@ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define MASTER_PLL_DIV 15 -#define MASTER_PLL_MUL 162 -#define MAIN_PLL_DIV 2 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 - -/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (1 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC_CS 0 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c new file mode 100644 index 0000000000..91a64b4158 --- /dev/null +++ b/arch/arm/boards/pm9261/lowlevel_init.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC; + + cfg->smc_cs = 0; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_3 | + AT91_SDRAMC_DBW_32 | + (1 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (3 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (1 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 1200; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile index eb072c0161..b6460c3982 100644 --- a/arch/arm/boards/pm9263/Makefile +++ b/arch/arm/boards/pm9263/Makefile @@ -1 +1,5 @@ obj-y += init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o diff --git a/arch/arm/boards/pm9263/config.h b/arch/arm/boards/pm9263/config.h index 322c1f3d30..906661330d 100644 --- a/arch/arm/boards/pm9263/config.h +++ b/arch/arm/boards/pm9263/config.h @@ -3,107 +3,4 @@ #define AT91_MAIN_CLOCK 18432000 -#define MASTER_PLL_DIV 6 -#define MASTER_PLL_MUL 65 -#define MAIN_PLL_DIV 2 /* 2 or 4 */ - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_OUT | \ - AT91_PMC_PLLCOUNT | /* PLL Counter */ \ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -#if (MAIN_PLL_DIV == 2) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91SAM9_PMC_MDIV_2 | \ - AT91_PMC_PDIV_1) -#else -/* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_CSS_SLOW | \ - AT91_PMC_PRES_1 | \ - AT91RM9200_PMC_MDIV_3 | \ - AT91_PMC_PDIV_1) -/* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_CSS_PLLA | \ - AT91_PMC_PRES_1 | \ - AT91RM9200_PMC_MDIV_3 | \ - AT91_PMC_PDIV_1) -#endif -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ - AT91_MATRIX_EBI0_CS1A_SDRAMC) - -/* SDRAM */ -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* tWR - Write Recovery Delay */ \ - (7 << 12) | /* tRC - Row Cycle Delay */ \ - (2 << 16) | /* tRP - Row Precharge Delay */ \ - (2 << 20) | /* tRCD - Row to Column Delay */ \ - (5 << 24) | /* tRAS - Active to Precharge Delay */ \ - (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC_CS 0 -#define CONFIG_SYS_SMC_SETUP_VAL \ - (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ - AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) -#define CONFIG_SYS_SMC_PULSE_VAL \ - (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ - AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) -#define CONFIG_SYS_SMC_CYCLE_VAL \ - (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) -#define CONFIG_SYS_SMC_MODE_VAL \ - (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ - AT91_SMC_DBW_16 | \ - AT91_SMC_TDFMODE | \ - AT91_SMC_TDF_(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_PROCRST | \ - AT91_RSTC_RSTTYP_WAKEUP | \ - AT91_RSTC_RSTTYP_WATCHDOG) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ - AT91_WDT_WDV | \ - AT91_WDT_WDDIS | \ - AT91_WDT_WDD) - - #endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c index 0be5cf54b5..4afa09536d 100644 --- a/arch/arm/boards/pm9263/init.c +++ b/arch/arm/boards/pm9263/init.c @@ -89,7 +89,7 @@ static void pm_add_device_nand(void) } static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c new file mode 100644 index 0000000000..6336d51063 --- /dev/null +++ b/arch/arm/boards/pm9263/lowlevel_init.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_PLL_DIV 6 +#define MASTER_PLL_MUL 65 +#define MAIN_PLL_DIV 2 /* 2 or 4 */ + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 0; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE | + AT91_SMC_TDF_(6); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11); + cfg->smc_setup = + AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10); + + cfg->pmc_mor = + AT91_PMC_MOSCEN | + (255 << 8); /* Main Oscillator Start-up Time */ + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_OUT | + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (2 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + + if (MAIN_PLL_DIV == 2) { + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + } else { + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91RM9200_PMC_MDIV_3 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91RM9200_PMC_MDIV_3 | + AT91_PMC_PDIV_1; + } + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x3AA; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* tWR - Write Recovery Delay */ + (7 << 12) | /* tRC - Row Cycle Delay */ + (2 << 16) | /* tRP - Row Precharge Delay */ + (2 << 20) | /* tRCD - Row to Column Delay */ + (5 << 24) | /* tRAS - Active to Precharge Delay */ + (8 << 28); /* tXSR - Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = 1200; + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c index 8e29f62e8e..720099b125 100644 --- a/arch/arm/boards/pm9g45/init.c +++ b/arch/arm/boards/pm9g45/init.c @@ -113,7 +113,7 @@ static void __init pm9g45_add_device_usbh(void) {} #endif static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = 0, }; @@ -137,7 +137,7 @@ static void pm9g45_add_device_eth(void) static int pm9g45_mem_init(void) { - at91_add_device_sdram(128 * 1024 * 1024); + at91_add_device_sdram(0); return 0; } diff --git a/arch/arm/boards/qil-a9260/init.c b/arch/arm/boards/qil-a9260/init.c index 4977d3b75e..2e131fee8e 100644 --- a/arch/arm/boards/qil-a9260/init.c +++ b/arch/arm/boards/qil-a9260/init.c @@ -78,7 +78,7 @@ static void qil_a9260_add_device_mci(void) {} #ifdef CONFIG_CALAO_MB_QIL_A9260 static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; diff --git a/arch/arm/boards/sama5d3xek/Makefile b/arch/arm/boards/sama5d3xek/Makefile new file mode 100644 index 0000000000..db021eeb77 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/Makefile @@ -0,0 +1,2 @@ +obj-y += init.o +obj-$(CONFIG_W1) += hw_version.o diff --git a/arch/arm/boards/sama5d3xek/config.h b/arch/arm/boards/sama5d3xek/config.h new file mode 100644 index 0000000000..d97181032f --- /dev/null +++ b/arch/arm/boards/sama5d3xek/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/sama5d3xek/env/bin/init_board b/arch/arm/boards/sama5d3xek/env/bin/init_board new file mode 100644 index 0000000000..f3d417e356 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/env/bin/init_board @@ -0,0 +1,15 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +splash=/env/splash.png + +if [ -f ${splash} -a -e /dev/fb0 ]; then + splash -o ${splash} + fb0.enable=1 +fi + +exit 1 diff --git a/arch/arm/boards/sama5d3xek/env/config b/arch/arm/boards/sama5d3xek/env/config new file mode 100644 index 0000000000..375e90d74a --- /dev/null +++ b/arch/arm/boards/sama5d3xek/env/config @@ -0,0 +1,44 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp-barebox +global.dhcp.vendor_id=barebox-sama5d3xek +global.dhcp.client_id="${sama5d3xcm.board}-${sama5d3xcm.vendor}" + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=nfs +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net +# can be either 'nfs', 'tftp', 'nand' or empty +oftree_loc=nfs + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type +ubiroot=rootfs + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +kernelimage=zImage +#kernelimage=uImage +#kernelimage=Image +#kernelimage=Image.lzo + +nand_device=atmel_nand +nand_parts="256k(at91bootstrap),384k(barebox)ro,256k@768k(bareboxenv),256k(bareboxenv2),128k@1536k(oftree),5M@2M(kernel),-@8M(rootfs)" +rootfs_mtdblock_nand=7 + +m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)" + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c new file mode 100644 index 0000000000..a9fcf7dc11 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/hw_version.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include <common.h> +#include <fs.h> +#include <fcntl.h> +#include <libbb.h> +#include <asm/armlinux.h> +#include <of.h> +#include <libfdt.h> + +#include "hw_version.h" + +enum board_type { + BOARD_TYPE_MB, + BOARD_TYPE_DM, + BOARD_TYPE_CPU, +}; + +static struct board_info { + char *name; + enum board_type type; + unsigned char id; +} board_list[] = { + {"SAMA5D3x-MB", BOARD_TYPE_MB, 0}, + {"SAMA5D3x-DM", BOARD_TYPE_DM, 1}, + {"SAMA5D31-CM", BOARD_TYPE_CPU, 2}, + {"SAMA5D33-CM", BOARD_TYPE_CPU, 3}, + {"SAMA5D34-CM", BOARD_TYPE_CPU, 4}, + {"SAMA5D35-CM", BOARD_TYPE_CPU, 5}, + {"PDA-DM", BOARD_TYPE_DM, 7}, +}; + +static struct board_info* get_board_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(board_list); i++) { + char *bname = board_list[i].name; + if (strncmp(name, bname, strlen(bname)) == 0) + return &board_list[i]; + } + + return NULL; +} + +static struct vendor_info { + char *name; + enum vendor_id id; +} vendor_list[] = { + {"EMBEST", VENDOR_EMBEST}, + {"FLEX", VENDOR_FLEX}, + {"RONETIX", VENDOR_RONETIX}, + {"COGENT", VENDOR_COGENT}, + {"PDA", VENDOR_PDA}, +}; + +static struct vendor_info* get_vendor_info_by_name(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vendor_list); i++) { + char *vname = vendor_list[i].name; + if (strncmp(name, vname, strlen(vname)) == 0) + return &vendor_list[i]; + } + + return NULL; +} + +#define BOARD_NAME_LEN 12 +#define VENDOR_NAME_LEN 10 +#define VENDOR_COUNTRY_LEN 2 + +struct one_wire_info { + u8 total_bytes; + u8 vendor_name[VENDOR_NAME_LEN]; + u8 vendor_country[VENDOR_COUNTRY_LEN]; + u8 board_name[BOARD_NAME_LEN]; + u8 year; + u8 week; + u8 revision_board; + u8 revision_schema; + u8 revision_bom; + u8 checksum_l; + u8 checksum_h; +}__attribute__ ((packed)); + +static int at91sama5d3xek_read_w1(const char *file, struct one_wire_info *info) +{ + int fd; + int ret; + + fd = open(file, O_RDONLY); + if (fd < 0) { + ret = fd; + goto err; + } + + ret = read_full(fd, info, sizeof(*info)); + if (ret < 0) + goto err_open; + + if (ret < sizeof(*info)) { + ret = -EINVAL; + goto err_open; + } + + pr_debug("total_bytes = %d\n", info->total_bytes); + pr_debug("vendor_name = %s\n", info->vendor_name); + pr_debug("vendor_country = %.2s\n", info->vendor_country); + pr_debug("board_name = %s\n", info->board_name); + pr_debug("year = %d\n", info->year); + pr_debug("week = %d\n", info->week); + pr_debug("revision_board = %x\n", info->revision_board); + pr_debug("revision_schema = %x\n", info->revision_schema); + pr_debug("revision_bom = %x\n", info->revision_bom); + pr_debug("checksum_l = %x\n", info->checksum_l); + pr_debug("checksum_h = %x\n", info->checksum_h); + + ret = 0; + +err_open: + close(fd); +err: + if (ret) + pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret)); + return ret; +} + +static u32 sn = 0; +static u32 rev = 0; + +bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid) +{ + return ((sn >> 5) & 0x1f) == vid; +} + +bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid) +{ + return ((sn >> 25) & 0x1f) == vid; +} + +bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid) +{ + return ((sn >> 15) & 0x1f) == vid; +} + +static void at91sama5d3xek_devices_detect_one(const char *name) +{ + struct one_wire_info info; + struct board_info* binfo; + struct vendor_info* vinfo; + struct device_d *dev = NULL; + char str[16]; + char *bname, *vname; + u8 vendor_id = 0; + + if (at91sama5d3xek_read_w1(name, &info)) + return; + + binfo = get_board_info_by_name(info.board_name); + + if (!binfo) { + pr_err("board %s no supported\n", info.board_name); + return; + } + bname = binfo->name; + + vinfo = get_vendor_info_by_name(info.vendor_name); + vname = info.vendor_name; + if (vinfo) { + vendor_id = vinfo->id; + vname = vinfo->name; + } + + switch (binfo->type) { + case BOARD_TYPE_CPU: + dev = add_generic_device_res("sama5d3xcm", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= (binfo->id & 0x1f); + sn |= ((vendor_id & 0x1f) << 5); + rev |= (info.revision_board - 'A'); + rev |= (((info.revision_schema - '0') & 0x3) << 15); + pr_info("CM"); + break; + case BOARD_TYPE_MB: + dev = add_generic_device_res("sama5d3xmb", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= ((binfo->id & 0x1f) << 20); + sn |= ((vendor_id & 0x1f) << 25); + rev |= ((info.revision_board - 'A') << 10); + rev |= (((info.revision_schema - '0') & 0x3) << 21); + pr_info("MB"); + break; + case BOARD_TYPE_DM: + dev = add_generic_device_res("sama5d3xdm", DEVICE_ID_SINGLE, NULL, 0, NULL); + if (!dev) + return; + sn |= ((binfo->id & 0x1f) << 10); + sn |= ((vendor_id & 0x1f) << 15); + rev |= ((info.revision_board - 'A') << 5); + rev |= (((info.revision_schema - '0') & 0x3) << 18); + pr_info("DM"); + break; + } + + pr_info(": %s [%c%c] from %s\n", + bname, info.revision_board, info.revision_schema, vname); + + dev_add_param_fixed(dev, "vendor", vname); + dev_add_param_fixed(dev, "board", bname); + sprintf(str, "%.2s", info.vendor_country); + dev_add_param_fixed(dev, "country", str); + sprintf(str, "%d", info.year); + dev_add_param_fixed(dev, "year", str); + sprintf(str, "%d", info.week); + dev_add_param_fixed(dev, "week", str); + sprintf(str, "%c", info.revision_board); + dev_add_param_fixed(dev, "revision_board", str); + sprintf(str, "%c", info.revision_schema); + dev_add_param_fixed(dev, "revision_schema", str); + sprintf(str, "%c", info.revision_bom); + dev_add_param_fixed(dev, "revision_bom", str); +} + +void at91sama5d3xek_devices_detect_hw(void) +{ + at91sama5d3xek_devices_detect_one("/dev/ds24310"); + at91sama5d3xek_devices_detect_one("/dev/ds28ec200"); + at91sama5d3xek_devices_detect_one("/dev/ds24330"); + + pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); + armlinux_set_revision(rev); + armlinux_set_serial(sn); +} diff --git a/arch/arm/boards/sama5d3xek/hw_version.h b/arch/arm/boards/sama5d3xek/hw_version.h new file mode 100644 index 0000000000..ed9ea88d42 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/hw_version.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __HW_REVISION_H__ +#define __HW_REVISION_H__ + +enum vendor_id { + VENDOR_UNKNOWN = 0, + VENDOR_EMBEST = 1, + VENDOR_FLEX = 2, + VENDOR_RONETIX = 3, + VENDOR_COGENT = 4, + VENDOR_PDA = 5, +}; + +#ifdef CONFIG_W1 +bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid); +bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid); +bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid); +void at91sama5d3xek_devices_detect_hw(void); +#else +bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid) +{ + return false; +} + +bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid) +{ + return false; +} + +bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid) +{ + return false; +} + +void at91sama5d3xek_devices_detect_hw(void) {} +#endif + +#endif /* __HW_REVISION_H__ */ diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c new file mode 100644 index 0000000000..110a83f803 --- /dev/null +++ b/arch/arm/boards/sama5d3xek/init.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <sizes.h> +#include <linux/mtd/nand.h> +#include <mach/board.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_smc.h> +#include <gpio.h> +#include <mach/io.h> +#include <mach/at91_pmc.h> +#include <mach/at91_rstc.h> +#include <mach/at91sam9x5_matrix.h> +#include <input/qt1070.h> +#include <readkey.h> +#include <poller.h> +#include <linux/w1-gpio.h> +#include <w1_mac_address.h> +#include <spi/spi.h> +#include <linux/clk.h> +#include <linux/phy.h> +#include <linux/micrel_phy.h> + +#include "hw_version.h" + +struct w1_gpio_platform_data w1_pdata = { + .pin = AT91_PIN_PE25, + .ext_pullup_enable_pin = -EINVAL, + .is_open_drain = 0, +}; + +#if defined(CONFIG_NAND_ATMEL) +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = -EINVAL, + .enable_pin = -EINVAL, + .ecc_mode = NAND_ECC_HW, + .pmecc_sector_size = 512, + .pmecc_corr_cap = 4, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#endif + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config cm_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 6, + .nrd_pulse = 4, + .ncs_write_pulse = 5, + .nwe_pulse = 3, + + .read_cycle = 6, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 1, +}; + +static void ek_add_device_nand(void) +{ + struct clk *clk = clk_get(NULL, "smc_clk"); + + clk_enable(clk); + + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + cm_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + cm_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &cm_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} +#else +static void ek_add_device_nand(void) {} +#endif + +#if defined(CONFIG_DRIVER_NET_MACB) +static struct at91_ether_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static bool used_23 = false; +static bool used_43 = false; + +static int ek_register_mac_address_23(int id) +{ + if (used_23) + return -EBUSY; + + used_23 = true; + + return w1_local_mac_address_register(id, "tml", "w1-23-0"); +} + +static int ek_register_mac_address_43(int id) +{ + if (used_43) + return -EBUSY; + + used_43 = true; + + return w1_local_mac_address_register(id, "tml", "w1-43-0"); +} + +static void ek_add_device_eth(void) +{ + if (w1_local_mac_address_register(0, "tml", "w1-2d-0")) + if (ek_register_mac_address_23(0)) + ek_register_mac_address_43(0); + + if (ek_register_mac_address_23(1)) + ek_register_mac_address_43(1); + + at91_add_device_eth(1, &macb_pdata); +} +#else +static void ek_add_device_eth(void) {} +#endif + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +/* + * LCD Controller + */ +static struct fb_videomode at91_tft_vga_modes[] = { + { + .name = "LG", + .refresh = 60, + .xres = 800, .yres = 480, + .pixclock = KHZ2PICOS(33260), + + .left_margin = 88, .right_margin = 168, + .upper_margin = 8, .lower_margin = 37, + .hsync_len = 128, .vsync_len = 2, + + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +/* Default output mode is TFT 24 bit */ +#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) + +/* Driver datas */ +static struct atmel_lcdfb_platform_data ek_lcdc_data = { + .lcdcon_is_backlight = true, + .default_bpp = 16, + .default_dmacon = ATMEL_LCDC_DMAEN, + .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, + .guard_time = 9, + .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, + .mode_list = at91_tft_vga_modes, + .num_modes = ARRAY_SIZE(at91_tft_vga_modes), +}; + +static void ek_add_device_lcdc(void) +{ + at91_add_device_lcdc(&ek_lcdc_data); +} + +#else +static void ek_add_device_lcdc(void) {} +#endif + +#if defined(CONFIG_MCI_ATMEL) +/* + * MCI (SD/MMC) + */ +static struct atmel_mci_platform_data mci0_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PD17, + .wp_pin = -EINVAL, +}; + +static struct atmel_mci_platform_data mci1_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PD18, + .wp_pin = -EINVAL, +}; + +static void ek_add_device_mci(void) +{ + /* MMC0 */ + at91_add_device_mci(0, &mci0_data); + /* MMC1 */ + at91_add_device_mci(1, &mci1_data); +} +#else +static void ek_add_device_mci(void) {} +#endif + +#if defined(CONFIG_I2C_GPIO) +struct qt1070_platform_data qt1070_pdata = { + .irq_pin = AT91_PIN_PE31, +}; + +static struct i2c_board_info i2c_devices[] = { + { + .platform_data = &qt1070_pdata, + I2C_BOARD_INFO("qt1070", 0x1b), + }, +}; + +static void ek_add_device_i2c(void) +{ + at91_set_gpio_input(qt1070_pdata.irq_pin, 0); + at91_set_deglitch(qt1070_pdata.irq_pin, 1); + at91_add_device_i2c(1, i2c_devices, ARRAY_SIZE(i2c_devices)); + at91_add_device_i2c(0, NULL, 0); +} +#else +static void ek_add_device_i2c(void) {} +#endif + +#if defined(CONFIG_DRIVER_SPI_ATMEL) +static const struct spi_board_info ek_spi_devices[] = { + { + .name = "m25p80", + .chip_select = 0, + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 0, + } +}; + +static unsigned spi0_standard_cs[] = { AT91_PIN_PD13 }; +static struct at91_spi_platform_data spi_pdata = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +}; + +static void ek_add_device_spi(void) +{ + spi_register_board_info(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + at91_add_device_spi(0, &spi_pdata); +} +#else +static void ek_add_device_spi(void) {} +#endif + +#ifdef CONFIG_LED_GPIO +struct gpio_led leds[] = { + { + .gpio = AT91_PIN_PE24, + .active_low = 1, + .led = { + .name = "d1", + }, + }, { + .gpio = AT91_PIN_PE25, + .active_low = 1, + .led = { + .name = "d2", + }, + }, +}; + +static void ek_add_led(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(leds); i++) { + at91_set_gpio_output(leds[i].gpio, leds[i].active_low); + led_gpio_register(&leds[i]); + } + led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); +} +#else +static void ek_add_led(void) {} +#endif + +static int at91sama5d3xek_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(at91sama5d3xek_mem_init); + +static void ek_add_device_w1(void) +{ + at91_set_gpio_input(w1_pdata.pin, 0); + at91_set_multi_drive(w1_pdata.pin, 1); + add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); + + at91sama5d3xek_devices_detect_hw(); +} + +#ifdef CONFIG_POLLER +/* + * The SiI9022A (HDMI) and QT1070 share the same irq + * but if the SiI9022A is not reset the irq is pull down + * So do it. As the SiI9022A need 1s to reset (500ms up then 500ms down then up) + * do it poller to do not slow down the boot + */ +static int hdmi_reset_pin = AT91_PIN_PC31; +static uint64_t hdmi_reset_start; +struct poller_struct hdmi_poller; + +static void hdmi_on_poller(struct poller_struct *poller) +{ + if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND)) + return; + + gpio_set_value(hdmi_reset_pin, 1); + + poller_unregister(poller); + ek_add_device_i2c(); +} + +static void hdmi_off_poller(struct poller_struct *poller) +{ + if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND)) + return; + + gpio_set_value(hdmi_reset_pin, 0); + + hdmi_reset_start = get_time_ns(); + poller->func = hdmi_on_poller; +} + +static void ek_add_device_hdmi(void) +{ + at91_set_gpio_output(hdmi_reset_pin, 1); + hdmi_reset_start = get_time_ns(); + hdmi_poller.func = hdmi_off_poller; + + poller_register(&hdmi_poller); +} +#else +static void ek_add_device_hdmi(void) +{ + ek_add_device_i2c(); +} +#endif + +static int at91sama5d3xek_devices_init(void) +{ + ek_add_device_w1(); + ek_add_device_hdmi(); + ek_add_device_nand(); + ek_add_led(); + ek_add_device_eth(); + ek_add_device_spi(); + ek_add_device_mci(); + ek_add_device_lcdc(); + + armlinux_set_bootparams((void *)(SAMA5_DDRCS + 0x100)); + + devfs_add_partition("nand0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw"); + dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap"); + devfs_add_partition("nand0", SZ_256K, SZ_256K + SZ_128K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_512K + SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + devfs_add_partition("nand0", SZ_1M, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw1"); + dev_add_bb_dev("env_raw1", "env1"); + + return 0; +} +device_initcall(at91sama5d3xek_devices_init); + +static int at91sama5d3xek_console_init(void) +{ + at91_register_uart(0, 0); + at91_register_uart(2, 0); + return 0; +} +console_initcall(at91sama5d3xek_console_init); diff --git a/arch/arm/boards/telit-evk-pro3/Makefile b/arch/arm/boards/telit-evk-pro3/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/telit-evk-pro3/config.h b/arch/arm/boards/telit-evk-pro3/config.h new file mode 100644 index 0000000000..7aeff30e8c --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 6000000 /* 6.000 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi b/arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi new file mode 100644 index 0000000000..1987492df7 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:rootfs ubi.mtd=nand0.rootfs rootfstype=ubifs" diff --git a/arch/arm/boards/telit-evk-pro3/env/init/config-board b/arch/arm/boards/telit-evk-pro3/env/init/config-board new file mode 100644 index 0000000000..741b90213f --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/init/config-board @@ -0,0 +1,8 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=evk-pro3 +global.linux.bootargs.base="console=ttyS0,115200" +global.boot.default=nand-ubi diff --git a/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand new file mode 100644 index 0000000000..58e859bb96 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="0xC0000(nand0.bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),3M(nand0.kernel),-(nand0.rootfs)" +kernelname="atmel_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/telit-evk-pro3/env/init/usb b/arch/arm/boards/telit-evk-pro3/env/init/usb new file mode 100644 index 0000000000..47429f50a4 --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/env/init/usb @@ -0,0 +1,40 @@ +#!/bin/sh + +# Connect PC31 to GND to enable DFU +gpio_dfu=95 +gpio_name="PC31" +gpio_wait=5 + +product_id=0x1234 +vendor_id=0x4321 + +dfu_config="/dev/nand0.bootstrap.bb(bootstrap)sr,/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r" + +echo + +if [ $at91_udc0.vbus != 1 ]; then + echo "No USB Device cable plugged, normal boot" + exit +fi + +gpio_get_value ${gpio_dfu} +if [ $? = 0 ]; then + echo "${gpio_name} low value detected wait ${gpio_wait}s" + timeout -s -a ${gpio_wait} + + if [ $at91_udc0.vbus != 1 ]; then + echo "No USB Device cable plugged, normal boot" + exit + fi + + gpio_get_value ${gpio_dfu} + if [ $? = 0 ]; then + echo "Start DFU Mode" + dfu ${dfu_config} -P ${product_id} -V ${vendor_id} + exit + fi +fi + +global.autoboot_timeout=16 +echo "enable tty over USB Device, increase the boot delay to ${global.autoboot_timeout}s" +usbserial diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c new file mode 100644 index 0000000000..d5f1b3ea2e --- /dev/null +++ b/arch/arm/boards/telit-evk-pro3/init.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2013 Fabio Porcedda <fabio.porcedda@gmail.com>, Telit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <asm/armlinux.h> +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <linux/clk.h> +#include <mach/at91_rstc.h> +#include <mach/at91sam9_smc.h> +#include <mach/board.h> +#include <mach/io.h> +#include <nand.h> + +#define BOOTSTRAP_SIZE 0xC0000 + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, + .det_pin = -EINVAL, + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .on_flash_bbt = 1, +}; + +static struct sam9_smc_config evk_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 2, +}; + +static void evk_add_device_nand(void) +{ + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(0, 3, &evk_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .phy_interface = PHY_INTERFACE_MODE_RMII, + .phy_addr = 0, +}; + +static void evk_phy_reset(void) +{ + unsigned long rstc; + struct clk *clk = clk_get(NULL, "macb_clk"); + + clk_enable(clk); + + at91_set_gpio_input(AT91_PIN_PA14, 0); + at91_set_gpio_input(AT91_PIN_PA15, 0); + at91_set_gpio_input(AT91_PIN_PA17, 0); + at91_set_gpio_input(AT91_PIN_PA25, 0); + at91_set_gpio_input(AT91_PIN_PA26, 0); + at91_set_gpio_input(AT91_PIN_PA28, 0); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0d << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)) + ; + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN); +} + +/* + * MCI (SD/MMC) + */ +#if defined(CONFIG_MCI_ATMEL) +static struct atmel_mci_platform_data __initdata evk_mci_data = { + .bus_width = 4, + .detect_pin = AT91_PIN_PA27, + .wp_pin = AT91_PIN_PA25, +}; + +static void evk_usb_add_device_mci(void) +{ + at91_add_device_mci(0, &evk_mci_data); +} +#else +static void evk_usb_add_device_mci(void) {} +#endif + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata evk_usbh_data = { + .ports = 2, + .vbus_pin = { -EINVAL, -EINVAL }, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata evk_udc_data = { + .vbus_pin = AT91_PIN_PC4, + .pullup_pin = -EINVAL, /* pull-up driven by UDC */ +}; + +static int evk_mem_init(void) +{ + at91_add_device_sdram(0); + + return 0; +} +mem_initcall(evk_mem_init); + +static int evk_devices_init(void) +{ + evk_add_device_nand(); + evk_phy_reset(); + at91_add_device_eth(0, &macb_pdata); + at91_add_device_usbh_ohci(&evk_usbh_data); + at91_add_device_udc(&evk_udc_data); + evk_usb_add_device_mci(); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + + devfs_add_partition("nand0", 0x00000, BOOTSTRAP_SIZE, + DEVFS_PARTITION_FIXED, "bootstrap_raw"); + dev_add_bb_dev("bootstrap_raw", "bootstrap"); + devfs_add_partition("nand0", BOOTSTRAP_SIZE, SZ_256K, + DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", BOOTSTRAP_SIZE + SZ_256K, SZ_128K, + DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + devfs_add_partition("nand0", BOOTSTRAP_SIZE + SZ_256K + SZ_128K, + SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1"); + dev_add_bb_dev("env_raw1", "env1"); + + return 0; +} +device_initcall(evk_devices_init); + +static int evk_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(evk_console_init); diff --git a/arch/arm/boards/tny-a926x/Makefile b/arch/arm/boards/tny-a926x/Makefile index eb072c0161..36ea09fca8 100644 --- a/arch/arm/boards/tny-a926x/Makefile +++ b/arch/arm/boards/tny-a926x/Makefile @@ -1 +1,10 @@ obj-y += init.o + +bootstrap-$(CONFIG_MACH_TNY_A9263) = tny_a9263_bootstrap.o +obj-$(CONFIG_AT91_BOOTSTRAP) += $(bootstrap-y) + +lowlevel_init-$(CONFIG_MACH_TNY_A9263) = tny_a9263_lowlevel_init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c index 5fe653173a..4228254e3a 100644 --- a/arch/arm/boards/tny-a926x/init.c +++ b/arch/arm/boards/tny-a926x/init.c @@ -113,7 +113,7 @@ static void tny_a9260_add_device_nand(void) #ifdef CONFIG_DRIVER_NET_MACB static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; @@ -160,16 +160,31 @@ static struct spi_board_info tny_a9g20_lpw_spi_devices[] = { }, }; -static int spi0_standard_cs[] = { AT91_PIN_PC11 }; -struct at91_spi_platform_data spi0_pdata = { - .chipselect = spi0_standard_cs, - .num_chipselect = ARRAY_SIZE(spi0_standard_cs), +static struct spi_board_info tny_a9263_spi_devices[] = { + { + .name = "mtd_dataflash", + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, }; -static int spi1_standard_cs[] = { AT91_PIN_PC3 }; -struct at91_spi_platform_data spi1_pdata = { - .chipselect = spi1_standard_cs, - .num_chipselect = ARRAY_SIZE(spi1_standard_cs), +static int tny_a9263_spi0_standard_cs[] = { AT91_PIN_PA5 }; +struct at91_spi_platform_data tny_a9263_spi0_pdata = { + .chipselect = tny_a9263_spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(tny_a9263_spi0_standard_cs), +}; + +static int tny_a9g20_spi0_standard_cs[] = { AT91_PIN_PC11 }; +struct at91_spi_platform_data tny_a9g20_spi0_pdata = { + .chipselect = tny_a9g20_spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(tny_a9g20_spi0_standard_cs), +}; + +static int tny_a9g20_spi1_standard_cs[] = { AT91_PIN_PC3 }; +struct at91_spi_platform_data tny_a9g20_spi1_pdata = { + .chipselect = tny_a9g20_spi1_standard_cs, + .num_chipselect = ARRAY_SIZE(tny_a9g20_spi1_standard_cs), }; static void __init ek_add_device_udc(void) @@ -182,17 +197,19 @@ static void __init ek_add_device_udc(void) static void __init ek_add_device_spi(void) { - if (machine_is_tny_a9263()) - return; + if (machine_is_tny_a9263()) { + spi_register_board_info(tny_a9263_spi_devices, + ARRAY_SIZE(tny_a9263_spi_devices)); + at91_add_device_spi(0, &tny_a9263_spi0_pdata); - if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) { + } else if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) { spi_register_board_info(tny_a9g20_lpw_spi_devices, ARRAY_SIZE(tny_a9g20_lpw_spi_devices)); - at91_add_device_spi(1, &spi1_pdata); + at91_add_device_spi(1, &tny_a9g20_spi1_pdata); } else { spi_register_board_info(tny_a9g20_spi_devices, ARRAY_SIZE(tny_a9g20_spi_devices)); - at91_add_device_spi(0, &spi0_pdata); + at91_add_device_spi(0, &tny_a9g20_spi0_pdata); } } diff --git a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c new file mode 100644 index 0000000000..368c67744f --- /dev/null +++ b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <bootstrap.h> +#include <mach/bootstrap.h> + +#ifdef CONFIG_MTD_DATAFLASH +void * bootstrap_board_read_dataflash(void) +{ + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); +} +#endif diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c new file mode 100644 index 0000000000..1b146da625 --- /dev/null +++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_CLOCK 180 + +#if MASTER_CLOCK == 200 +#define MASTER_PLL_MUL 100 +#else +#define MASTER_PLL_MUL 90 +#endif +#define MASTER_PLL_DIV 6 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 3; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_8 | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_TDF_(2); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3); + cfg->smc_setup = + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0); + + cfg->pmc_mor = AT91_PMC_OSCBYPASS; + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (0 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NC_9 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (8 << 28); /* Exit Self Refresh to Active Delay */ + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = (MASTER_CLOCK * 7); + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} diff --git a/arch/arm/boards/usb-a926x/Makefile b/arch/arm/boards/usb-a926x/Makefile index eb072c0161..e314dd5b03 100644 --- a/arch/arm/boards/usb-a926x/Makefile +++ b/arch/arm/boards/usb-a926x/Makefile @@ -1 +1,10 @@ obj-y += init.o + +bootstrap-$(CONFIG_MACH_USB_A9263) = usb_a9263_bootstrap.o +obj-$(CONFIG_AT91_BOOTSTRAP) += $(bootstrap-y) + +lowlevel_init-$(CONFIG_MACH_USB_A9263) = usb_a9263_lowlevel_init.o + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) + +pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c index 95ac6a80ce..0383280b65 100644 --- a/arch/arm/boards/usb-a926x/init.c +++ b/arch/arm/boards/usb-a926x/init.c @@ -51,6 +51,7 @@ static void usb_a9260_set_board_type(void) armlinux_set_architecture(MACH_TYPE_USB_A9260); } +#if defined(CONFIG_NAND_ATMEL) static struct atmel_nand_data nand_pdata = { .ale = 21, .cle = 22, @@ -111,9 +112,13 @@ static void usb_a9260_add_device_nand(void) at91_add_device_nand(&nand_pdata); } +#else +static void usb_a9260_add_device_nand(void) {} +#endif +#if defined(CONFIG_DRIVER_NET_MACB) static struct at91_ether_platform_data macb_pdata = { - .is_rmii = 1, + .phy_interface = PHY_INTERFACE_MODE_RMII, .phy_addr = -1, }; @@ -149,6 +154,16 @@ static void usb_a9260_phy_reset(void) AT91_RSTC_URSTEN); } +static void usb_a9260_add_device_eth(void) +{ + usb_a9260_phy_reset(); + at91_add_device_eth(0, &macb_pdata); +} +#else +static void usb_a9260_add_device_eth(void) {} +#endif + +#if defined(CONFIG_DRIVER_SPI_ATMEL) static const struct spi_board_info usb_a9263_spi_devices[] = { { .name = "mtd_dataflash", @@ -191,6 +206,9 @@ static void usb_a9260_add_spi(void) at91_add_device_spi(1, &spi_a9g20_pdata); } } +#else +static void usb_a9260_add_spi(void) {} +#endif #if defined(CONFIG_MCI_ATMEL) static struct atmel_mci_platform_data __initdata usb_a9260_mci_data = { @@ -205,11 +223,21 @@ static void usb_a9260_add_device_mci(void) static void usb_a9260_add_device_mci(void) {} #endif +#if defined(CONFIG_USB_OHCI) static struct at91_usbh_data ek_usbh_data = { .ports = 2, .vbus_pin = { -EINVAL, -EINVAL }, }; +static void usb_a9260_add_device_usb(void) +{ + at91_add_device_usbh_ohci(&ek_usbh_data); +} +#else +static void usb_a9260_add_device_usb(void) {} +#endif + +#ifdef CONFIG_USB_GADGET_DRIVER_AT91 /* * USB Device port */ @@ -225,7 +253,11 @@ static void __init ek_add_device_udc(void) at91_add_device_udc(&ek_udc_data); } +#else +static void __init ek_add_device_udc(void) {} +#endif +#ifdef CONFIG_LED_GPIO struct gpio_led led = { .gpio = AT91_PIN_PB21, .led = { @@ -241,6 +273,9 @@ static void __init ek_add_led(void) at91_set_gpio_output(led.gpio, led.active_low); led_gpio_register(&led); } +#else +static void ek_add_led(void) {} +#endif static int usb_a9260_mem_init(void) { @@ -356,11 +391,10 @@ static void usb_a9260_device_dab_mmx(void) {} static int usb_a9260_devices_init(void) { usb_a9260_add_device_nand(); - usb_a9260_phy_reset(); - at91_add_device_eth(0, &macb_pdata); usb_a9260_add_device_mci(); + usb_a9260_add_device_eth(); usb_a9260_add_spi(); - at91_add_device_usbh_ohci(&ek_usbh_data); + usb_a9260_add_device_usb(); ek_add_device_udc(); ek_add_led(); ek_add_device_button(); @@ -382,6 +416,7 @@ static int usb_a9260_devices_init(void) } device_initcall(usb_a9260_devices_init); +#ifndef CONFIG_CONSOLE_NONE static int usb_a9260_console_init(void) { struct device_d *dev; @@ -398,3 +433,4 @@ static int usb_a9260_console_init(void) return 0; } console_initcall(usb_a9260_console_init); +#endif diff --git a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c new file mode 100644 index 0000000000..368c67744f --- /dev/null +++ b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <bootstrap.h> +#include <mach/bootstrap.h> + +#ifdef CONFIG_MTD_DATAFLASH +void * bootstrap_board_read_dataflash(void) +{ + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); +} +#endif diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c new file mode 100644 index 0000000000..f6dc58e3f6 --- /dev/null +++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <init.h> +#include <mach/hardware.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91_lowlevel_init.h> + +#define MASTER_CLOCK 180 + +#if MASTER_CLOCK == 200 +#define MASTER_PLL_MUL 100 +#else +#define MASTER_PLL_MUL 90 +#endif +#define MASTER_PLL_DIV 6 + +void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg) +{ + /* Disable Watchdog */ + cfg->wdt_mr = + AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | + AT91_WDT_WDV | + AT91_WDT_WDDIS | + AT91_WDT_WDD; + + /* define PDC[31:16] as DATA[31:16] */ + cfg->ebi_pio_pdr = 0xFFFF0000; + /* no pull-up for D[31:16] */ + cfg->ebi_pio_ppudr = 0xFFFF0000; + /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ + cfg->ebi_csa = + AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | + AT91_MATRIX_EBI0_CS1A_SDRAMC; + + cfg->smc_cs = 3; + cfg->smc_mode = + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_DBW_8 | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_TDF_(2); + cfg->smc_cycle = + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5); + cfg->smc_pulse = + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3); + cfg->smc_setup = + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0); + + cfg->pmc_mor = AT91_PMC_OSCBYPASS; + cfg->pmc_pllar = + AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ + AT91_PMC_PLLCOUNT | /* PLL Counter */ + (0 << 28) | /* PLL Clock Frequency Range */ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV); + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr1 = + AT91_PMC_CSS_SLOW | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + /* PCK/2 = MCK Master Clock from PLLA */ + cfg->pmc_mckr2 = + AT91_PMC_CSS_PLLA | + AT91_PMC_PRES_1 | + AT91SAM9_PMC_MDIV_2 | + AT91_PMC_PDIV_1; + + /* SDRAM */ + /* SDRAMC_TR - Refresh Timer register */ + cfg->sdrc_tr1 = 0x13C; + /* SDRAMC_CR - Configuration register*/ + cfg->sdrc_cr = + AT91_SDRAMC_NR_13 | + AT91_SDRAMC_NB_4 | + AT91_SDRAMC_CAS_2 | + AT91_SDRAMC_DBW_32 | + (2 << 8) | /* Write Recovery Delay */ + (7 << 12) | /* Row Cycle Delay */ + (2 << 16) | /* Row Precharge Delay */ + (2 << 20) | /* Row to Column Delay */ + (5 << 24) | /* Active to Precharge Delay */ + (8 << 28); /* Exit Self Refresh to Active Delay */ + + if (IS_ENABLED(CONFIG_AT91_HAVE_SRAM_128M)) + cfg->sdrc_cr |= AT91_SDRAMC_NC_10; + else + cfg->sdrc_cr |= AT91_SDRAMC_NC_9; + + /* Memory Device Register -> SDRAM */ + cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM; + /* SDRAM_TR */ + cfg->sdrc_tr2 = (MASTER_CLOCK * 7); + + /* user reset enable */ + cfg->rstc_rmr = + AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_RSTTYP_WAKEUP | + AT91_RSTC_RSTTYP_WATCHDOG; +} |