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| author | Lucas Stach <l.stach@pengutronix.de> | 2020-09-30 15:24:17 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-10-07 10:04:39 +0200 |
| commit | 276d0460f008b3dff7fdd6ce413cf6dafbfdd8d7 (patch) | |
| tree | 3e551878d7d7412d2a8408bb9c2a74da205dea47 /arch/arm/boards | |
| parent | f4a853de505063e7eb59f9cee42c855bea143823 (diff) | |
| download | barebox-276d0460f008b3dff7fdd6ce413cf6dafbfdd8d7.tar.gz barebox-276d0460f008b3dff7fdd6ce413cf6dafbfdd8d7.tar.xz | |
ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order
This way we end up with the fastest DDR speed when training is finished
and don't need to rely on TF-A to switch into a higher DDR speed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards')
| -rw-r--r-- | arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c index b164bdec07..8d6cc389ba 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_FREQ2_INIT7(0), 0x0006004a }, /* boot start point */ - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 + { DDRC_MSTR2(0), 0x0 }, }; /* PHY Initialize Configuration */ @@ -1941,12 +1941,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fsp_cfg = lpddr4_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), }, { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), - }, { /* P1 400mts 1D */ .drate = 400, .fw_type = FW_1D_IMAGE, @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = lpddr4_fsp2_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), }, }; |