diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-16 14:01:09 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-16 14:01:09 +0100 |
| commit | bf38ac7b89dee71d14d4d65e9ad0d0cb727cbb98 (patch) | |
| tree | 3cf8336e5c2c6341120a2b68f8bb7a5df385fb64 /arch/arm/boards | |
| parent | 38c75d0f112d4e8bc3762cd8d0b6dbae3cf7e441 (diff) | |
| parent | 4f2ac27e2503e15bffdebca4757e02638686fe94 (diff) | |
| download | barebox-bf38ac7b89dee71d14d4d65e9ad0d0cb727cbb98.tar.gz barebox-bf38ac7b89dee71d14d4d65e9ad0d0cb727cbb98.tar.xz | |
Merge branch 'for-next/imx'
Conflicts:
arch/arm/boards/guf-neso/lowlevel.c
arch/arm/boards/pcm038/lowlevel.c
commands/Makefile
Diffstat (limited to 'arch/arm/boards')
58 files changed, 958 insertions, 652 deletions
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 0b450d64e7..a8d172c0ff 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -23,7 +23,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx51-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> @@ -45,6 +45,7 @@ #include <mach/iim.h> #include <mach/clock-imx51_53.h> #include <mach/imx5.h> +#include <mach/revision.h> #include "ccxmx51.h" diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c index f04615d888..c947a1ee97 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51js.c +++ b/arch/arm/boards/ccxmx51/ccxmx51js.c @@ -20,7 +20,7 @@ #include <init.h> #include <mci.h> #include <asm/armlinux.h> -#include <mach/imx-regs.h> +#include <mach/imx51-regs.h> #include <mach/iomux-mx51.h> #include <mach/devices-imx51.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c index bf3cbc375a..92e8df2b9f 100644 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -22,7 +22,7 @@ #include <init.h> #include <driver.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <asm/armlinux.h> #include <asm/barebox-arm.h> #include <asm-generic/sections.h> @@ -250,18 +250,3 @@ void __bare_init nand_boot(void) imx_nand_load_image(_text, barebox_image_size); } #endif - -static int eukrea_cpuimx25_core_init(void) { - /* enable UART1, FEC, SDHC, USB & I2C clock */ - writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR0) | (1 << 6) | (1 << 23) - | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28), - MX25_CCM_BASE_ADDR + CCM_CGCR0); - writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR1) | (1 << 23) | (1 << 15) - | (1 << 13), MX25_CCM_BASE_ADDR + CCM_CGCR1); - writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR2) | (1 << 14), - MX25_CCM_BASE_ADDR + CCM_CGCR2); - - return 0; -} - -core_initcall(eukrea_cpuimx25_core_init); diff --git a/arch/arm/boards/eukrea_cpuimx25/flash_header.c b/arch/arm/boards/eukrea_cpuimx25/flash_header.c index 344c7ffc13..9102c2a371 100644 --- a/arch/arm/boards/eukrea_cpuimx25/flash_header.c +++ b/arch/arm/boards/eukrea_cpuimx25/flash_header.c @@ -23,7 +23,7 @@ */ #include <common.h> #include <mach/imx-flash-header.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <asm/barebox-arm-head.h> void __naked __flash_header_start go(void) diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 8d6cd1f982..36ce98bc69 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -19,7 +19,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <io.h> @@ -56,15 +56,15 @@ void __bare_init __naked reset(void) common_reset(); /* restart the MPLL and wait until it's stable */ - writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27), - MX25_CCM_BASE_ADDR + CCM_CCTL); - while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {}; + writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27), + MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); + while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {}; /* Configure dividers and ARM clock source * ARM @ 400 MHz * AHB @ 133 MHz */ - writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); /* Enable UART1 / FEC / */ /* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0); @@ -117,10 +117,10 @@ void __bare_init __naked reset(void) writel(0x1, 0xb8003000); /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2); + r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); r &= ~0xf; r |= 0x1; - writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2); + writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -128,22 +128,22 @@ void __bare_init __naked reset(void) board_init_lowlevel_return(); /* Init Mobile DDR */ - writel(0x0000000E, ESDMISC); - writel(0x00000004, ESDMISC); + writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops)); - writel(0x0029572B, ESDCFG0); - writel(0x92210000, ESDCTL0); + writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400); - writel(0xA2210000, ESDCTL0); + writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR); writeb(0xda, MX25_CSD0_BASE_ADDR); - writel(0xB2210000, ESDCTL0); + writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); - writel(0x82216080, ESDCTL0); + writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index cff4f77985..c89ce8a192 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -21,7 +21,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <fec.h> #include <notifier.h> #include <mach/gpio.h> @@ -194,7 +194,6 @@ static int eukrea_cpuimx27_devices_init(void) #endif imx27_add_nand(&nand_info); - PCCR0 |= PCCR0_I2C1_EN; i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); imx27_add_i2c0(NULL); @@ -223,11 +222,16 @@ device_initcall(eukrea_cpuimx27_devices_init); static int eukrea_cpuimx27_console_init(void) { + uint32_t val; + #ifdef CONFIG_DRIVER_SERIAL_IMX imx27_add_uart0(); #endif /* configure 8 bit UART on cs3 */ - FMCR &= ~0x2; + val = readl(MX27_SYSCTRL_BASE_ADDR + MX27_FMCR); + val &= ~0x2; + writel(val, MX27_SYSCTRL_BASE_ADDR + MX27_FMCR); + imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000); #ifdef CONFIG_DRIVER_SERIAL_NS16550 add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf, diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index 1983d480f9..4ee6efb84e 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -1,6 +1,7 @@ #include <config.h> #include <asm-generic/memory_layout.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> +#include <mach/esdctl.h> #include <asm/barebox-arm-head.h> #define writel(val, reg) \ @@ -9,10 +10,10 @@ str r1, [r0]; #if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB -#define ROWS0 ESDCTL_ROW14 +#define ROWS0 ESDCTL0_ROW14 #define CFG0 0x0029572D #elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB -#define ROWS0 ESDCTL_ROW13 +#define ROWS0 ESDCTL0_ROW13 #define CFG0 0x00095728 #endif @@ -22,20 +23,26 @@ /* * DDR on CSD0 */ - writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */ - - writel(0x55555555, DSCR(3)) /* Set the driving strength */ - writel(0x55555555, DSCR(5)) - writel(0x55555555, DSCR(6)) - writel(0x00005005, DSCR(7)) - writel(0x15555555, DSCR(8)) - - writel(0x00000004, ESDMISC) /* Initial reset */ - writel(CFG0, ESDCFG0) - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + /* Enable DDR SDRAM operation */ + writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0) + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xa0000f00 mov r1, #0 @@ -45,7 +52,8 @@ subs r2, #1 bne 1b - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xA0000033 mov r1, #0xda strb r1, [r0] @@ -56,7 +64,9 @@ #endif mov r1, #0xff strb r1, [r0] - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) .endm .section ".text_bare_init","ax" @@ -67,23 +77,26 @@ reset: common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* disable mpll/spll */ - ldr r0, =CSCR + ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR ldr r1, [r0] bic r1, r1, #0x03 str r1, [r0] - + /* * pll clock initialization - see section 3.4.3 of the i.MX27 manual */ - writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */ - writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */ - writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + /* MPLL = 399 MHz */ + writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 240 MHz */ + writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) + writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) /* add some delay here */ mov r1, #0x1000 @@ -91,12 +104,14 @@ reset: bne 1b /* clock gating enable */ - writel(0x00050f08, GPCR) + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) /* peripheral clock divider */ - writel(0x130400c3, PCDR0) /* FIXME */ - writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz */ + /* FIXME */ + writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0) + /* PERDIV1=08 @133 MHz */ + writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1) + /* PERDIV1=04 @266 MHz */ /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 53cc428c84..fdbc26ab42 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -41,7 +41,7 @@ #include <mach/gpio.h> #include <mach/imx-nand.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/iomux-mx35.h> #include <mach/iomux-v3.h> #include <mach/imx-ipu-fb.h> @@ -246,14 +246,14 @@ static int eukrea_cpuimx35_core_init(void) u32 reg; /* enable clock for I2C1, SDHC1, USB and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); - reg |= 0x3 << CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT; - reg |= 0x3 << CCM_CGR1_I2C1_SHIFT, - reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); - reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2); - reg |= 0x3 << CCM_CGR2_USB_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_SDHC1_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT, + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); + reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT; + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* @@ -345,10 +345,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c index 26752d1cbf..6fa9c8b0ef 100644 --- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c +++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c @@ -1,6 +1,6 @@ #include <common.h> #include <mach/imx-flash-header.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <asm/barebox-arm-head.h> void __naked __flash_header_start go(void) diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index 8689f9ee30..052333503d 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/cache-l2x0.h> @@ -41,10 +41,10 @@ static void __bare_init __naked insdram(void) uint32_t r; /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); r &= ~(0xf << 28); r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); @@ -105,27 +105,27 @@ void __bare_init __naked reset(void) * End of ARM1136 init */ - writel(0x003F4208, ccm_base + CCM_CCMR); + writel(0x003F4208, ccm_base + MX35_CCM_CCMR); /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); - writel(0x00001000, ccm_base + CCM_PDR0); + writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); + writel(0x00001000, ccm_base + MX35_CCM_PDR0); - r = readl(ccm_base + CCM_CGR0); + r = readl(ccm_base + MX35_CCM_CGR0); r |= 0x00300000; - writel(r, ccm_base + CCM_CGR0); + writel(r, ccm_base + MX35_CCM_CGR0); - r = readl(ccm_base + CCM_CGR1); + r = readl(ccm_base + MX35_CCM_CGR1); r |= 0x00030C00; r |= 0x00000003; - writel(r, ccm_base + CCM_CGR1); + writel(r, ccm_base + MX35_CCM_CGR1); /* enable watchdog asap */ - r = readl(ccm_base + CCM_CGR2); + r = readl(ccm_base + MX35_CCM_CGR2); r |= 0x03000000; - writel(r, ccm_base + CCM_CGR2); + writel(r, ccm_base + MX35_CCM_CGR2); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; @@ -137,22 +137,22 @@ void __bare_init __naked reset(void) board_init_lowlevel_return(); /* Init Mobile DDR */ - writel(0x0000000E, ESDMISC); - writel(0x00000004, ESDMISC); + writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops)); - writel(0x0009572B, ESDCFG0); - writel(0x92220000, ESDCTL0); + writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); - writel(0xA2220000, ESDCTL0); + writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR); writeb(0xda, MX35_CSD0_BASE_ADDR); - writel(0xB2220000, ESDCTL0); + writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); - writel(0x82228080, ESDCTL0); + writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c index 1279f8965a..ab0ff81d73 100644 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c @@ -19,7 +19,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx51-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c index a0ae938809..5ce2f8e290 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -21,7 +21,7 @@ #include <init.h> #include <driver.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <asm/armlinux.h> #include <asm-generic/sections.h> #include <asm/barebox-arm.h> @@ -167,8 +167,8 @@ static int imx25_3ds_fec_init(void) * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 */ - writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */ - writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */ + writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */ + writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */ #define FEC_ENABLE_GPIO 35 #define FEC_RESET_B_GPIO 104 @@ -215,7 +215,7 @@ static int imx25_devices_init(void) imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); - if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14)) + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); @@ -298,7 +298,7 @@ void __bare_init nand_boot(void) static int imx25_core_setup(void) { - writel(0x01010103, MX25_CCM_BASE_ADDR + CCM_PCDR2); + writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); return 0; } diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S index f911f9d7f8..fb980991a6 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -18,7 +18,7 @@ */ #include <asm-generic/memory_layout.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/barebox-arm-head.h> @@ -66,9 +66,9 @@ reset: str r1, [r0, #MX25_CCM_MCR] /* enable all the clocks */ - writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0) - writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1) - writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2) + writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0) + writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1) + writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2) writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) /* Skip SDRAM initialization if we run from RAM */ diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c index 7cd61f9e96..5bcb24cf45 100644 --- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c @@ -236,7 +236,7 @@ static int mx28_evk_devices_init(void) imx_enable_enetclk(); mx28_evk_fec_reset(); - add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0x4000, + add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000, IORESOURCE_MEM, &fec_info); return 0; diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c index 9a01424402..7da031ab6b 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c @@ -41,12 +41,13 @@ #include <mach/gpio.h> #include <mach/weim.h> #include <mach/imx-nand.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/iomux-mx35.h> #include <mach/iomux-v3.h> #include <mach/imx-ipu-fb.h> #include <mach/generic.h> #include <mach/devices-imx35.h> +#include <mach/revision.h> #include <i2c/i2c.h> #include <mfd/mc13xxx.h> @@ -143,7 +144,7 @@ static int f3s_devices_init(void) /* CS0: Nor Flash */ imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -281,10 +282,10 @@ static int f3s_core_init(void) imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00); /* enable clock for I2C1 and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); - reg |= 0x3 << CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << CCM_CGR1_I2C1_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* diff --git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c index 66763dbf2a..076b816491 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c +++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c @@ -1,6 +1,6 @@ #include <common.h> #include <mach/imx-flash-header.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <asm/barebox-arm-head.h> void __naked __flash_header_start go(void) diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S index e5d0feb18f..dada5f3fd5 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -17,7 +17,7 @@ * */ -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/cache-l2x0.h> @@ -98,27 +98,27 @@ reset: ldr r0, CCM_BASE_ADDR_W ldr r2, CCM_CCMR_W - str r2, [r0, #CCM_CCMR] + str r2, [r0, #MX35_CCM_CCMR] ldr r3, MPCTL_PARAM_532_W /* consumer path*/ /* Set MPLL, arm clock and ahb clock */ - str r3, [r0, #CCM_MPCTL] + str r3, [r0, #MX35_CCM_MPCTL] ldr r1, PPCTL_PARAM_W - str r1, [r0, #CCM_PPCTL] + str r1, [r0, #MX35_CCM_PPCTL] ldr r1, CCM_PDR0_W - str r1, [r0, #CCM_PDR0] + str r1, [r0, #MX35_CCM_PDR0] - ldr r1, [r0, #CCM_CGR0] + ldr r1, [r0, #MX35_CCM_CGR0] orr r1, r1, #0x00300000 - str r1, [r0, #CCM_CGR0] + str r1, [r0, #MX35_CCM_CGR0] - ldr r1, [r0, #CCM_CGR1] + ldr r1, [r0, #MX35_CCM_CGR1] orr r1, r1, #0x00000C00 orr r1, r1, #0x00000003 - str r1, [r0, #CCM_CGR1] + str r1, [r0, #MX35_CCM_CGR1] /* Skip SDRAM initialization if we run from RAM */ cmp pc, #CSD0_BASE_ADDR @@ -140,13 +140,13 @@ reset: /* setup bank 0 */ mov r5, #0x00 mov r2, #0x00 - mov r1, #CSD0_BASE_ADDR + mov r1, #MX35_CSD0_BASE_ADDR bl setup_sdram_bank /* setup bank 1 */ mov r5, #0x00 mov r2, #0x00 - mov r1, #CSD1_BASE_ADDR + mov r1, #MX35_CSD1_BASE_ADDR bl setup_sdram_bank mov lr, fp diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c index 3a8e5eaf04..9db0ed9bef 100644 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ b/arch/arm/boards/freescale-mx51-pdk/board.c @@ -17,7 +17,7 @@ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx51-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> @@ -25,6 +25,7 @@ #include <partition.h> #include <fs.h> #include <fcntl.h> +#include <mach/bbu.h> #include <nand.h> #include <notifier.h> #include <spi/spi.h> @@ -37,7 +38,9 @@ #include <mach/generic.h> #include <mach/iomux-mx51.h> #include <mach/devices-imx51.h> +#include <mach/revision.h> #include <mach/iim.h> +#include <mach/imx-flash-header.h> static struct fec_platform_data fec_info = { .xcv_type = MII100, @@ -234,6 +237,10 @@ static void babbage_power_init(void) mdelay(50); } +#define DCD_NAME static struct imx_dcd_entry dcd_entry + +#include "dcd-data.h" + static int f3s_devices_init(void) { spi_register_board_info(mx51_babbage_spi_board_info, @@ -254,6 +261,9 @@ static int f3s_devices_init(void) armlinux_set_bootparams((void *)0x90000100); armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/disk0", + BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry)); + return 0; } diff --git a/arch/arm/boards/freescale-mx51-pdk/dcd-data.h b/arch/arm/boards/freescale-mx51-pdk/dcd-data.h new file mode 100644 index 0000000000..4dd6c0d26c --- /dev/null +++ b/arch/arm/boards/freescale-mx51-pdk/dcd-data.h @@ -0,0 +1,60 @@ + +DCD_NAME[] = { + { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, + { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, + { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, + { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, + { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, + { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, + { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, + { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, + { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, + { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, + { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, +}; + diff --git a/arch/arm/boards/freescale-mx51-pdk/flash_header.c b/arch/arm/boards/freescale-mx51-pdk/flash_header.c index c148eea4ff..f3f1e4bfd5 100644 --- a/arch/arm/boards/freescale-mx51-pdk/flash_header.c +++ b/arch/arm/boards/freescale-mx51-pdk/flash_header.c @@ -7,64 +7,9 @@ void __naked __flash_header_start go(void) barebox_arm_head(); } -struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { - { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, - { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, - { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, - { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, - { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, - { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, - { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, - { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, - { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, - { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, - { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, - { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, - { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, - { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, - { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, - { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, - { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, - { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, - { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, -}; +#define DCD_NAME struct imx_dcd_entry __dcd_entry_section dcd_entry + +#include "dcd-data.h" #define APP_DEST 0x90000000 diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c index f7d6e050a8..216d26a0a8 100644 --- a/arch/arm/boards/freescale-mx53-loco/board.c +++ b/arch/arm/boards/freescale-mx53-loco/board.c @@ -27,7 +27,7 @@ #include <generated/mach-types.h> -#include <mach/imx-regs.h> +#include <mach/imx53-regs.h> #include <mach/iomux-mx53.h> #include <mach/devices-imx53.h> #include <mach/generic.h> @@ -35,6 +35,9 @@ #include <mach/imx-nand.h> #include <mach/iim.h> #include <mach/imx5.h> +#include <mach/revision.h> +#include <mach/bbu.h> +#include <mach/imx-flash-header.h> #include <i2c/i2c.h> #include <mfd/mc34708.h> @@ -176,6 +179,10 @@ static void loco_ehci_init(void) add_generic_usb_ehci_device(1, MX53_OTG_BASE_ADDR + 0x200, NULL); } +#define DCD_NAME static struct imx_dcd_v2_entry dcd_entry + +#include "dcd-data.h" + static int loco_devices_init(void) { @@ -195,6 +202,9 @@ static int loco_devices_init(void) armlinux_set_bootparams((void *)0x70000100); armlinux_set_architecture(MACH_TYPE_MX53_LOCO); + imx53_bbu_internal_mmc_register_handler("mmc", "/dev/disk0", + BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry)); + return 0; } diff --git a/arch/arm/boards/freescale-mx53-loco/dcd-data.h b/arch/arm/boards/freescale-mx53-loco/dcd-data.h new file mode 100644 index 0000000000..9f95fb4b89 --- /dev/null +++ b/arch/arm/boards/freescale-mx53-loco/dcd-data.h @@ -0,0 +1,54 @@ + +DCD_NAME[] = { + { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), }, + { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), }, + { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), }, + { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), }, + { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), }, + { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), }, + { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), }, + { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), }, + { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), }, + { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), }, + { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, + { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), }, + { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), }, + { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), }, + { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, + { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, + { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, +}; diff --git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c index c2ab25582e..dc1162bac8 100644 --- a/arch/arm/boards/freescale-mx53-loco/flash_header.c +++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c @@ -23,59 +23,9 @@ void __naked __flash_header_start go(void) barebox_arm_head(); } -struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = { - { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), }, - { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), }, - { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), }, - { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), }, - { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), }, - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), }, - { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), }, - { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), }, - { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), }, - { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, - { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), }, - { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), }, - { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), }, - { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, - { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, - { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, -}; +#define DCD_NAME struct imx_dcd_v2_entry __dcd_entry_section dcd_entry + +#include "dcd-data.h" #define APP_DEST 0x70000000 diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c index 04831030a8..a5ad009106 100644 --- a/arch/arm/boards/freescale-mx53-smd/board.c +++ b/arch/arm/boards/freescale-mx53-smd/board.c @@ -27,7 +27,7 @@ #include <generated/mach-types.h> -#include <mach/imx-regs.h> +#include <mach/imx53-regs.h> #include <mach/iomux-mx53.h> #include <mach/devices-imx53.h> #include <mach/generic.h> diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c index ccc73182db..ce9874d85f 100644 --- a/arch/arm/boards/freescale-mx6-arm2/board.c +++ b/arch/arm/boards/freescale-mx6-arm2/board.c @@ -15,7 +15,7 @@ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx6-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index 25402d7c9c..da37e17b8f 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -17,7 +17,7 @@ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx6-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> @@ -200,7 +200,7 @@ static inline int imx6_iim_register_fec_ethaddr(void) return 0; } -static int sabrelite_spi_cs[] = {GPIO_PORTC + 19}; +static int sabrelite_spi_cs[] = {IMX_GPIO_NR(3, 19)}; static struct spi_imx_master sabrelite_spi_0_data = { .chipselect = sabrelite_spi_cs, diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c index 933a9cd057..5b1732631a 100644 --- a/arch/arm/boards/guf-cupid/board.c +++ b/arch/arm/boards/guf-cupid/board.c @@ -25,7 +25,7 @@ #include <driver.h> #include <environment.h> #include <fs.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <asm/armlinux.h> #include <mach/gpio.h> #include <io.h> @@ -117,7 +117,7 @@ static int cupid_devices_init(void) gpio_direction_output(GPIO_LCD_ENABLE, 0); gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); - reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -339,10 +339,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index a1b58cc3c8..f2e44af7a5 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/cache-l2x0.h> @@ -70,15 +70,15 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad u32 r1, r0; /* disable second SDRAM region to save power */ - r1 = readl(ESDCTL1); + r1 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1); r1 &= ~ESDCTL0_SDE; - writel(r1, ESDCTL1); + writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1); mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST; - writel(mode, ESDMISC); + writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST); - writel(mode, ESDMISC); + writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); /* wait for esdctl reset */ for (loop = 0; loop < 0x20000; loop++); @@ -89,16 +89,18 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | ESDCFGx_tRC_20; - writel(r1, ESDCFG0); + writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); /* enable SDRAM controller */ - writel(memsize | ESDCTL0_SMODE_NORMAL, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_NORMAL, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); /* Micron Datasheet Initialization Step 3: Wait 200us before first command */ for (loop = 0; loop < 1000; loop++); /* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */ - writel(memsize | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_PRECHARGE, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(r11, sdram_addr); /* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns) @@ -108,7 +110,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad /* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP * (at least 140ns) */ - writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(r11, r9); /* AUTO REFRESH #1 */ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ @@ -118,7 +121,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ /* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */ - writel(memsize | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_LOAD_MODE, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3)); /* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP @@ -133,7 +137,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad */ /* Now configure SDRAM-Controller and check that it works */ - writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, ESDCTL0); + writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); /* Freescale asks for first access to be a write to properly * initialize DQS pin-state and keepers @@ -155,10 +160,10 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad /* if both value are identical, we don't have 14 rows. assume 13 instead */ if (readl(r9) == readl(r9 + (1 << 25))) { - r0 = readl(ESDCTL0); + r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); r0 &= ~ESDCTL0_ROW_MASK; r0 |= ESDCTL0_ROW13; - writel(r0, ESDCTL0); + writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } /* So far we asssumed that we have 10 columns, verify this */ @@ -167,10 +172,10 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad /* if both value are identical, we don't have 10 cols. assume 9 instead */ if (readl(r9) == readl(r9 + (1 << 11))) { - r0 = readl(ESDCTL0); + r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); r0 &= ~ESDCTL0_COL_MASK; r0 |= ESDCTL0_COL9; - writel(r0, ESDCTL0); + writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } } @@ -181,7 +186,7 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad void __bare_init __naked reset(void) { u32 r0, r1; - void *iomuxc_base = (void *)IMX_IOMUXC_BASE; + void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR; int i; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; @@ -297,27 +302,27 @@ void __bare_init __naked reset(void) /* Configure clocks */ /* setup cpu/bus clocks */ - writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR); + writel(0x003f4208, MX35_CCM_BASE_ADDR + MX35_CCM_CCMR); /* configure MPLL */ - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); /* configure PPLL */ - writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL); + writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + MX35_CCM_PPCTL); /* configure core dividers */ - r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2); + r0 = MX35_PDR0_CCM_PER_AHB(1) | MX35_PDR0_HSP_PODF(2); - writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0); + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR0); /* configure clock-gates */ - r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0); + r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); r0 |= 0x00300000; - writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0); + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); + r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); r0 |= 0x00000c03; - writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1); + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); /* Configure SDRAM */ /* Try 32-Bit 256 MB DDR memory */ diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index 7adee929b0..200a2efc53 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -35,7 +35,7 @@ #include <mach/gpio.h> #include <mach/spi.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <mach/iomux-mx27.h> #include <mach/imx-nand.h> #include <mach/imx-pll.h> @@ -320,10 +320,10 @@ static int neso_pll(void) pllfunc(); /* clock gating enable */ - GPCR = 0x00050f08; + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); - PCDR0 = 0x130410c3; - PCDR1 = 0x09030911; + writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); + writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index d45a5b492a..ad414d9208 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/cache-l2x0.h> @@ -33,8 +33,6 @@ #ifdef CONFIG_NAND_IMX_BOOT static void __bare_init __naked insdram(void) { - PCCR1 |= PCCR1_NFC_BAUDEN; - /* setup a stack to be able to call imx_nand_load_image() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); @@ -57,10 +55,10 @@ void __bare_init __naked reset(void) common_reset(); /* ahb lite ip interface */ - AIPI1_PSR0 = 0x20040304; - AIPI1_PSR1 = 0xDFFBFCFB; - AIPI2_PSR0 = 0x00000000; - AIPI2_PSR1 = 0xFFFFFFFF; + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -70,30 +68,38 @@ void __bare_init __naked reset(void) /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ - - DSCR(3) = 0x55555555; /* Set the driving strength */ - DSCR(5) = 0x55555555; - DSCR(6) = 0x55555555; - DSCR(7) = 0x00005005; - DSCR(8) = 0x15555555; - - writel(0x00000004, ESDMISC); /* Initial reset */ - writel(0x006ac73a, ESDCFG0); - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); for (i = 0; i < 8; i++) writel(0, 0xa0000f00); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, 0xa0000033); writeb(0xff, 0xa1000000); writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S index 87e5312fb4..4c6cb67fd4 100644 --- a/arch/arm/boards/guf-neso/pll_init.S +++ b/arch/arm/boards/guf-neso/pll_init.S @@ -1,5 +1,5 @@ #include <config.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <mach/imx-pll.h> #include <linux/linkage.h> @@ -8,34 +8,37 @@ ldr r1, =val; \ str r1, [r0]; -#define CSCR_VAL CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_MCU_SEL | \ - CSCR_ARM_SRC_MPLL | \ - CSCR_SP_SEL | \ - CSCR_ARM_DIV(0) | \ - CSCR_FPM_EN | \ - CSCR_SPEN | \ - CSCR_MPEN | \ - CSCR_AHB_DIV(1) +#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_MCU_SEL | \ + MX27_CSCR_ARM_SRC_MPLL | \ + MX27_CSCR_SP_SEL | \ + MX27_CSCR_ARM_DIV(0) | \ + MX27_CSCR_FPM_EN | \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN | \ + MX27_CSCR_AHB_DIV(1) ENTRY(neso_pll_init) + /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) - writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) ldr r2, =16000 1: diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c index 22406beb5a..ca566c831a 100644 --- a/arch/arm/boards/imx21ads/imx21ads.c +++ b/arch/arm/boards/imx21ads/imx21ads.c @@ -21,7 +21,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx21-regs.h> #include <asm/armlinux.h> #include <asm-generic/sections.h> #include <asm/barebox-arm.h> @@ -95,10 +95,10 @@ static int imx21ads_timing_init(void) imx21_setup_eimcs(4, 0x0, 0x0); imx21_setup_eimcs(5, 0x0, 0x0); - temp = PCDR0; + temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0); temp &= ~0xF000; temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */ - PCDR0 = temp; + writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0); return 0; } @@ -193,7 +193,6 @@ console_initcall(mx21ads_console_init); #ifdef CONFIG_NAND_IMX_BOOT void __bare_init nand_boot(void) { - PCCR0 |= PCCR0_NFC_EN; imx_nand_load_image(_text, barebox_image_size); board_init_lowlevel_return(); } diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S index 0cb8aaf950..e52cac1443 100644 --- a/arch/arm/boards/imx21ads/lowlevel_init.S +++ b/arch/arm/boards/imx21ads/lowlevel_init.S @@ -15,7 +15,7 @@ #include <config.h> #include <asm-generic/memory_layout.h> -#include <mach/imx-regs.h> +#include <mach/imx21-regs.h> #include <asm/barebox-arm-head.h> .section ".text_bare_init","ax" @@ -30,17 +30,17 @@ reset: * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21 * reference manual. */ - ldr r0, =AIPI1_PSR0 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0 ldr r1, =0x00040304 str r1, [r0] - ldr r0, =AIPI1_PSR1 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1 ldr r1, =0xfffbfcfb str r1, [r0] - ldr r0, =AIPI2_PSR0 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0 ldr r1, =0x3ffc0000 str r1, [r0] - ldr r0, =AIPI2_PSR1 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1 ldr r1, =0xffffffff str r1, [r0] @@ -48,11 +48,11 @@ reset: * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable * the clock to peripherals. */ - ldr r0, =CSCR + ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR ldr r1, =0x17180607 str r1, [r0] - ldr r0, =PCCR1 + ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1 ldr r1, =0x0e000000 str r1, [r0] @@ -65,7 +65,7 @@ reset: * CSD1 not required, because the MX21ADS board only contains 64Mbyte. * CS3 can therefore be made available. */ - ldr r0, =FMCR + ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR ldr r1, =0xffffffc9 str r1, [r0] @@ -79,7 +79,7 @@ reset: 1: /* Precharge */ - ldr r0, =SDCTL0 + ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0 ldr r1, =0x92120300 str r1, [r0] ldr r2, =0xc0200000 @@ -113,7 +113,7 @@ reset: str r1, [r0] /* Set NFC_CLK to 24MHz */ - ldr r0, =PCDR0 + ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0 ldr r1, =0x6419a007 str r1, [r0] diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c index 22c6e40f9f..f41b155d16 100644 --- a/arch/arm/boards/imx27ads/imx27ads.c +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -18,7 +18,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <asm/armlinux.h> #include <io.h> #include <fec.h> diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S index 1bebb1d0a4..2dc34b5967 100644 --- a/arch/arm/boards/imx27ads/lowlevel_init.S +++ b/arch/arm/boards/imx27ads/lowlevel_init.S @@ -5,7 +5,7 @@ */ #include <config.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <asm/barebox-arm-head.h> #define writel(val, reg) \ @@ -118,13 +118,13 @@ reset: common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* disable mpll/spll */ - ldr r0, =CSCR + ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR ldr r1, [r0] bic r1, r1, #0x03 str r1, [r0] @@ -136,15 +136,16 @@ reset: * with 1.2 V core voltage! Find out if this is * documented somewhere. */ - writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */ - writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */ + writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */ + writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */ /* * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz * System clock (HCLK) = 133 MHz */ - writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) /* add some delay here */ mov r1, #0x1000 @@ -152,13 +153,14 @@ reset: bne 1b /* clock gating enable */ - writel(0x00050f08, GPCR) + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) /* peripheral clock divider */ - writel(0x23C8F403, PCDR0) /* FIXME */ - writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz * - * / + /* FIXME */ + writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0) + /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz */ + writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1) /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 bls 1f diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index 5413ea801c..1ffd890dd6 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -21,7 +21,7 @@ #include <init.h> #include <driver.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <asm/armlinux.h> #include <asm-generic/sections.h> #include <asm/barebox-arm.h> @@ -75,8 +75,8 @@ static iomux_v3_cfg_t karo_tx25_padsd_fec[] = { MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, }; -#define TX25_FEC_PWR_GPIO (GPIO_PORTD | 9) -#define TX25_FEC_RST_GPIO (GPIO_PORTD | 7) +#define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9) +#define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7) static void noinline gpio_fec_active(void) { @@ -108,7 +108,7 @@ static int tx25_devices_init(void) imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); - if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14)) + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); @@ -217,9 +217,9 @@ static struct imx_fb_videomode stk5_fb_mode = { .pcr = PCR_TFT | PCR_COLOR | PCR_FLMPOL | PCR_LPPOL | PCR_SCLK_SEL, }; -#define STK5_LCD_BACKLIGHT_GPIO (GPIO_PORTA | 26) -#define STK5_LCD_RESET_GPIO (GPIO_PORTB | 4) -#define STK5_LCD_POWER_GPIO (GPIO_PORTB | 5) +#define STK5_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 26) +#define STK5_LCD_RESET_GPIO IMX_GPIO_NR(2, 4) +#define STK5_LCD_POWER_GPIO IMX_GPIO_NR(2, 5) static void tx25_fb_enable(int enable) { diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index 2d09fd70d1..9c5cc5c8ee 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx25-regs.h> #include <mach/esdctl.h> #include <io.h> #include <mach/imx-nand.h> @@ -45,8 +45,8 @@ static void __bare_init __naked insdram(void) static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, uint32_t esdcfg) { - uint32_t esdctlreg = ESDCTL0; - uint32_t esdcfgreg = ESDCFG0; + uint32_t esdctlreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0; + uint32_t esdcfgreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0; if (base == 0x90000000) { esdctlreg += 8; @@ -121,12 +121,12 @@ void __bare_init __naked reset(void) writel(0x1, 0xb8003000); /* configure ARM clk */ - writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); /* enable all the clocks */ - writel(0x1fffffff, MX25_CCM_BASE_ADDR + CCM_CGCR0); - writel(0xffffffff, MX25_CCM_BASE_ADDR + CCM_CGCR1); - writel(0x000fdfff, MX25_CCM_BASE_ADDR + CCM_CGCR2); + writel(0x1fffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0); + writel(0xffffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1); + writel(0x000fdfff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -136,9 +136,9 @@ void __bare_init __naked reset(void) /* set to 3.3v SDRAM */ writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454); - writel(ESDMISC_RST, ESDMISC); + writel(ESDMISC_RST, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); - while (!(readl(ESDMISC) & (1 << 31))); + while (!(readl(MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC) & (1 << 31))); #define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \ ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL) diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index 961787669b..766e77b247 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -393,7 +393,7 @@ void base_board_init(void) tx28_get_ethaddr(); imx_enable_enetclk(); - add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0x4000, + add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000, IORESOURCE_MEM, &fec_info); ret = register_persistent_environment(); diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c index 3ee0ebd66e..dd377c140a 100644 --- a/arch/arm/boards/karo-tx51/tx51.c +++ b/arch/arm/boards/karo-tx51/tx51.c @@ -18,7 +18,7 @@ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx51-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/karo-tx53/Makefile b/arch/arm/boards/karo-tx53/Makefile index b56ce7f50d..2f45976184 100644 --- a/arch/arm/boards/karo-tx53/Makefile +++ b/arch/arm/boards/karo-tx53/Makefile @@ -1,2 +1,5 @@ obj-y += board.o obj-y += flash_header.o +pbl-y += flash_header.o +obj-y += lowlevel.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c index c8509bebcb..8f87c9c9a8 100644 --- a/arch/arm/boards/karo-tx53/board.c +++ b/arch/arm/boards/karo-tx53/board.c @@ -25,7 +25,7 @@ #include <generated/mach-types.h> -#include <mach/imx-regs.h> +#include <mach/imx53-regs.h> #include <mach/iomux-mx53.h> #include <mach/devices-imx53.h> #include <mach/generic.h> @@ -33,6 +33,8 @@ #include <mach/imx-nand.h> #include <mach/iim.h> #include <mach/imx5.h> +#include <mach/imx-flash-header.h> +#include <mach/bbu.h> #include <asm/armlinux.h> #include <io.h> @@ -99,7 +101,10 @@ static iomux_v3_cfg_t tx53_pads[] = { static int tx53_mem_init(void) { - arm_add_mem_device("ram0", 0x70000000, SZ_1G); + if (IS_ENABLED(CONFIG_TX53_REV_1011)) + arm_add_mem_device("ram0", 0x70000000, SZ_1G); + else + arm_add_mem_device("ram0", 0x70000000, SZ_512M); return 0; } @@ -203,6 +208,14 @@ static inline void tx53_fec_init(void) ARRAY_SIZE(tx53_fec_pads)); } +#define DCD_NAME_1011 static struct imx_dcd_v2_entry dcd_entry_1011 + +#include "dcd-data-1011.h" + +#define DCD_NAME_XX30 static u32 dcd_entry_xx30 + +#include "dcd-data-xx30.h" + static int tx53_devices_init(void) { imx53_iim_register_fec_ethaddr(); @@ -214,6 +227,14 @@ static int tx53_devices_init(void) armlinux_set_bootparams((void *)0x70000100); armlinux_set_architecture(MACH_TYPE_TX53); + /* rev xx30 can boot from nand or USB */ + imx53_bbu_internal_nand_register_handler("nand-xx30", + BBU_HANDLER_FLAG_DEFAULT, (void *)dcd_entry_xx30, sizeof(dcd_entry_xx30), SZ_512K); + + /* rev 1011 can boot from MMC/SD, other bootsource currently unknown */ + imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0", + 0, (void *)dcd_entry_1011, sizeof(dcd_entry_1011)); + return 0; } @@ -221,8 +242,25 @@ device_initcall(tx53_devices_init); static int tx53_part_init(void) { - devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); + const char *envdev; + + switch (imx_bootsource()) { + case bootsource_mmc: + devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); + envdev = "MMC"; + break; + case bootsource_nand: + default: + devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x80000, 0x100000, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + envdev = "NAND"; + break; + } + + printf("Using environment in %s\n", envdev); return 0; } @@ -232,7 +270,8 @@ static int tx53_console_init(void) { mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); - imx53_init_lowlevel(1000); + if (!IS_ENABLED(CONFIG_TX53_REV_XX30)) + imx53_init_lowlevel(1000); imx53_add_uart0(); return 0; diff --git a/arch/arm/boards/karo-tx53/dcd-data-1011.h b/arch/arm/boards/karo-tx53/dcd-data-1011.h new file mode 100644 index 0000000000..7034ff80de --- /dev/null +++ b/arch/arm/boards/karo-tx53/dcd-data-1011.h @@ -0,0 +1,94 @@ +DCD_NAME_1011[] = { + { .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), }, + { .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), }, + { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), }, + { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), }, + { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), }, + { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), }, + { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), }, + { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), }, + { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), }, + { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), }, + { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), }, + { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), }, + { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), }, + { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, + { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), }, + { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), }, + { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, + { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, + { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, + { .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), }, + { .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), }, +}; diff --git a/arch/arm/boards/karo-tx53/dcd-data-xx30.h b/arch/arm/boards/karo-tx53/dcd-data-xx30.h new file mode 100644 index 0000000000..cb982dc2e3 --- /dev/null +++ b/arch/arm/boards/karo-tx53/dcd-data-xx30.h @@ -0,0 +1,144 @@ + +#define DCD_ITEM(adr, val) cpu_to_be32(adr), cpu_to_be32(val) +#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (len) << 8 | 0x04) +#define DCD_CHECK_CMD(a, b, c) cpu_to_be32(a), cpu_to_be32(b), cpu_to_be32(c) + +/* + * This board uses advanced features of the DCD which do not corporate + * well with our flash header defines. The DCD consists of commands which + * have the length econded into them. Normally the DCDs only have a single + * command (DCD_COMMAND_WRITE_TAG) which is already part of struct + * imx_flash_header_v2. Now this board uses multiple commands, so we cannot + * calculate the command length using sizeof(dcd_entry). + */ + +DCD_NAME_XX30[] = { + DCD_ITEM(0x53fd4068, 0xffcc0fff), + DCD_ITEM(0x53fd406c, 0x000fffc3), + DCD_ITEM(0x53fd4070, 0x033c0000), + DCD_ITEM(0x53fd4074, 0x00000000), + DCD_ITEM(0x53fd4078, 0x00000000), + DCD_ITEM(0x53fd407c, 0x00fff033), + DCD_ITEM(0x53fd4080, 0x0f00030f), + DCD_ITEM(0x53fd4084, 0xfff00000), + DCD_ITEM(0x53fd4088, 0x00000000), + DCD_ITEM(0x53fa8174, 0x00000011), + DCD_ITEM(0x53fa8318, 0x00000011), + DCD_ITEM(0x63fd800c, 0x00000000), + DCD_ITEM(0x53fd4014, 0x00888944), + DCD_ITEM(0x53fd4018, 0x00016154), + DCD_ITEM(0x53fa8724, 0x04000000), + DCD_ITEM(0x53fa86f4, 0x00000000), + DCD_ITEM(0x53fa8714, 0x00000000), + DCD_ITEM(0x53fa86fc, 0x00000080), + DCD_ITEM(0x53fa8710, 0x00000000), + DCD_ITEM(0x53fa8708, 0x00000040), + DCD_ITEM(0x53fa8584, 0x00280000), + DCD_ITEM(0x53fa8594, 0x00280000), + DCD_ITEM(0x53fa8560, 0x00280000), + DCD_ITEM(0x53fa8554, 0x00280000), + DCD_ITEM(0x53fa857c, 0x00a80040), + DCD_ITEM(0x53fa8590, 0x00a80040), + DCD_ITEM(0x53fa8568, 0x00a80040), + DCD_ITEM(0x53fa8558, 0x00a80040), + DCD_ITEM(0x53fa8580, 0x00280040), + DCD_ITEM(0x53fa8578, 0x00280000), + DCD_ITEM(0x53fa8564, 0x00280040), + DCD_ITEM(0x53fa8570, 0x00280000), + DCD_ITEM(0x53fa858c, 0x000000c0), + DCD_ITEM(0x53fa855c, 0x000000c0), + DCD_ITEM(0x53fa8574, 0x00280000), + DCD_ITEM(0x53fa8588, 0x00280000), + DCD_ITEM(0x53fa86f0, 0x00280000), + DCD_ITEM(0x53fa8720, 0x00280000), + DCD_ITEM(0x53fa8718, 0x00280000), + DCD_ITEM(0x53fa871c, 0x00280000), + DCD_ITEM(0x53fa8728, 0x00280000), + DCD_ITEM(0x53fa872c, 0x00280000), + DCD_ITEM(0x63fd904c, 0x001f001f), + DCD_ITEM(0x63fd9050, 0x001f001f), + DCD_ITEM(0x63fd907c, 0x011e011e), + DCD_ITEM(0x63fd9080, 0x011f0120), + DCD_ITEM(0x63fd9088, 0x3a393d3b), + DCD_ITEM(0x63fd9090, 0x3f3f3f3f), + DCD_ITEM(0x63fd9018, 0x00011740), + DCD_ITEM(0x63fd9000, 0x83190000), + DCD_ITEM(0x63fd900c, 0x3f435316), + DCD_ITEM(0x63fd9010, 0xb66e0a63), + DCD_ITEM(0x63fd9014, 0x01ff00db), + DCD_ITEM(0x63fd902c, 0x000026d2), + DCD_ITEM(0x63fd9030, 0x00430f24), + DCD_ITEM(0x63fd9008, 0x1b221010), + DCD_ITEM(0x63fd9004, 0x00030012), + DCD_ITEM(0x63fd901c, 0x00008032), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x00408031), + DCD_ITEM(0x63fd901c, 0x055080b0), + DCD_ITEM(0x63fd9020, 0x00005800), + DCD_ITEM(0x63fd9058, 0x00011112), + DCD_ITEM(0x63fd90d0, 0x00000003), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00008040), + DCD_ITEM(0x63fd9040, 0x0539002b), + DCD_CHECK_CMD(0xcf000c04, 0x63fd9040, 0x00010000), + DCD_WR_CMD(0x24), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd901c, 0x00848231), + DCD_ITEM(0x63fd901c, 0x00000000), + DCD_ITEM(0x63fd9048, 0x00000001), + DCD_CHECK_CMD(0xcf000c04, 0x63fd9048, 0x00000001), + DCD_WR_CMD(0x2c), + DCD_ITEM(0x63fd901c, 0x00048031), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd907c, 0x90000000), + DCD_CHECK_CMD(0xcf000c04, 0x63fd907c, 0x90000000), + DCD_WR_CMD(0x2c), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x00000000), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd90a4, 0x00000010), + DCD_CHECK_CMD(0xcf000c04, 0x63fd90a4, 0x00000010), + DCD_WR_CMD(0x24), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd90a0, 0x00000010), + DCD_CHECK_CMD(0xcf000c04, 0x63fd90a0, 0x00000010), + DCD_WR_CMD(0x010c), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x00000000), + DCD_ITEM(0x53fa8004, 0x00194005), + DCD_ITEM(0x53fa819c, 0x00000000), + DCD_ITEM(0x53fa81a0, 0x00000000), + DCD_ITEM(0x53fa81a4, 0x00000000), + DCD_ITEM(0x53fa81a8, 0x00000000), + DCD_ITEM(0x53fa81ac, 0x00000000), + DCD_ITEM(0x53fa81b0, 0x00000000), + DCD_ITEM(0x53fa81b4, 0x00000000), + DCD_ITEM(0x53fa81b8, 0x00000000), + DCD_ITEM(0x53fa81dc, 0x00000000), + DCD_ITEM(0x53fa81e0, 0x00000000), + DCD_ITEM(0x53fa8228, 0x00000000), + DCD_ITEM(0x53fa822c, 0x00000000), + DCD_ITEM(0x53fa8230, 0x00000000), + DCD_ITEM(0x53fa8234, 0x00000000), + DCD_ITEM(0x53fa8238, 0x00000000), + DCD_ITEM(0x53fa84ec, 0x000000e4), + DCD_ITEM(0x53fa84f0, 0x000000e4), + DCD_ITEM(0x53fa84f4, 0x000000e4), + DCD_ITEM(0x53fa84f8, 0x000000e4), + DCD_ITEM(0x53fa84fc, 0x000000e4), + DCD_ITEM(0x53fa8500, 0x000000e4), + DCD_ITEM(0x53fa8504, 0x000000e4), + DCD_ITEM(0x53fa8508, 0x000000e4), + DCD_ITEM(0x53fa852c, 0x00000004), + DCD_ITEM(0x53fa8530, 0x00000004), + DCD_ITEM(0x53fa85a0, 0x00000004), + DCD_ITEM(0x53fa85a4, 0x00000004), + DCD_ITEM(0x53fa85a8, 0x000000e4), + DCD_ITEM(0x53fa85ac, 0x000000e4), + DCD_ITEM(0x53fa85b0, 0x00000004), +}; diff --git a/arch/arm/boards/karo-tx53/flash_header.c b/arch/arm/boards/karo-tx53/flash_header.c index 9b97fab2df..5c6aa53e47 100644 --- a/arch/arm/boards/karo-tx53/flash_header.c +++ b/arch/arm/boards/karo-tx53/flash_header.c @@ -20,109 +20,31 @@ void __naked __flash_header_start go(void) { - barebox_arm_head(); + barebox_arm_imx_fcb_head(); } /* * FIXME: These are the dcd values for a Ka-Ro TX53 1011 which * is not in production. It has 1GB DDR2 memory. */ -struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = { - { .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), }, - { .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), }, - { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), }, - { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), }, - { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), }, - { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), }, - { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), }, - { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), }, - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), }, - { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), }, - { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), }, - { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), }, - { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, - { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), }, - { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), }, - { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, - { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, - { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, - { .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), }, - { .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), }, -}; +#ifdef CONFIG_TX53_REV_1011 + +#define DCD_NAME_1011 struct imx_dcd_v2_entry __dcd_entry_section dcd_entry + +#include "dcd-data-1011.h" + +#elif defined(CONFIG_TX53_REV_XX30) + +#define DCD_NAME_XX30 u32 __dcd_entry_section dcd_entry + +#include "dcd-data-xx30.h" + +#endif + +#define APP_DEST 0x71000000 -#define APP_DEST 0x70000000 +int tx53_dcdentry_size = sizeof(dcd_entry); +void *tx53_dcd_entry = &dcd_entry; struct imx_flash_header_v2 __flash_header_section flash_header = { .header.tag = IVT_HEADER_TAG, @@ -142,6 +64,10 @@ struct imx_flash_header_v2 __flash_header_section flash_header = { .dcd.header.version = DCD_VERSION, .dcd.command.tag = DCD_COMMAND_WRITE_TAG, +#ifdef CONFIG_TX53_REV_1011 .dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)), +#elif defined(CONFIG_TX53_REV_XX30) + .dcd.command.length = cpu_to_be16(0x21c), +#endif .dcd.command.param = DCD_COMMAND_WRITE_PARAM, }; diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c new file mode 100644 index 0000000000..0ca164bda5 --- /dev/null +++ b/arch/arm/boards/karo-tx53/lowlevel.c @@ -0,0 +1,22 @@ +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx5.h> + +#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT + +void __naked reset(void) +{ + common_reset(); + + /* + * For the TX53 rev 8030 the SDRAM setup is not stable without + * the proper PLL setup. It will crash once we enable the MMU, + * so do the PLL setup here. + */ + if (IS_ENABLED(CONFIG_TX53_REV_XX30)) + imx53_init_lowlevel(800); + + board_init_lowlevel_return(); +} +#endif diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S index a6747c2482..f9ecce1141 100644 --- a/arch/arm/boards/pcm037/lowlevel_init.S +++ b/arch/arm/boards/pcm037/lowlevel_init.S @@ -17,9 +17,10 @@ * */ -#include <mach/imx-regs.h> +#include <mach/imx31-regs.h> #include <mach/imx-pll.h> #include <asm/barebox-arm-head.h> +#include <mach/esdctl.h> #define writel(val, reg) \ ldr r0, =reg; \ @@ -46,24 +47,30 @@ reset: common_reset r0 - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR) + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) DELAY 0x40000 - writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR) - writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR) - - writel(PDR0_CSI_PODF(0xff1) | \ - PDR0_PER_PODF(7) | \ - PDR0_HSP_PODF(3) | \ - PDR0_NFC_PODF(5) | \ - PDR0_IPG_PODF(1) | \ - PDR0_MAX_PODF(3) | \ - PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + CCM_PDR0) - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL) + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR) + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) + + writel(MX31_PDR0_CSI_PODF(0xff1) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0) + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | + IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL) + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL) /* Configure IOMUXC * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) @@ -96,19 +103,19 @@ clear_iomux: #elif defined CONFIG_PCM037_SDRAM_BANK0_256MB #define ROWS0 ESDCTL0_ROW14 #endif - writel(0x00000004, ESDMISC) - writel(0x006ac73a, ESDCFG0) - writel(0x90100000 | ROWS0, ESDCTL0) + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0) + writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS0, ESDCTL0) + writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x12344321, MX31_CSD0_BASE_ADDR) writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0xb0100000 | ROWS0, ESDCTL0) + writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33) writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS0, ESDCTL0) + writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR) - writel(0x0000000c, ESDMISC) + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) #ifndef CONFIG_PCM037_SDRAM_BANK1_NONE #if defined CONFIG_PCM037_SDRAM_BANK1_128MB @@ -116,18 +123,18 @@ clear_iomux: #elif defined CONFIG_PCM037_SDRAM_BANK1_256MB #define ROWS1 ESDCTL0_ROW14 #endif - writel(0x006ac73a, ESDCFG1) - writel(0x90100000 | ROWS1, ESDCTL1) + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1) + writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS1, ESDCTL1) + writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0x12344321, MX31_CSD1_BASE_ADDR) writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0xb0100000 | ROWS1, ESDCTL1) + writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33) writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS1, ESDCTL1) + writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR) - writel(0x0000000c, ESDMISC) + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) #endif #ifdef CONFIG_NAND_IMX_BOOT diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c index 1a1688d053..ff4089ad25 100644 --- a/arch/arm/boards/pcm037/pcm037.c +++ b/arch/arm/boards/pcm037/pcm037.c @@ -24,7 +24,7 @@ #include <fs.h> #include <environment.h> #include <usb/ulpi.h> -#include <mach/imx-regs.h> +#include <mach/imx31-regs.h> #include <mach/iomux-mx31.h> #include <asm/armlinux.h> #include <asm-generic/sections.h> @@ -96,7 +96,7 @@ static void pcm037_usb_init(void) /* Host 2 */ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8); tmp |= 1 << 11; - writel(tmp, IOMUXC_BASE + 0x8); + writel(tmp, MX31_IOMUXC_BASE_ADDR + 0x8); imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c index de86a06dfa..2f93c3127a 100644 --- a/arch/arm/boards/pcm038/lowlevel.c +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <io.h> @@ -34,8 +34,6 @@ #ifdef CONFIG_NAND_IMX_BOOT static void __bare_init __naked insdram(void) { - PCCR1 |= PCCR1_NFC_BAUDEN; - /* setup a stack to be able to call imx_nand_load_image() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); @@ -57,10 +55,10 @@ void __bare_init __naked reset(void) common_reset(); /* ahb lite ip interface */ - AIPI1_PSR0 = 0x20040304; - AIPI1_PSR1 = 0xDFFBFCFB; - AIPI2_PSR0 = 0x00000000; - AIPI2_PSR1 = 0xFFFFFFFF; + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -68,37 +66,46 @@ void __bare_init __naked reset(void) board_init_lowlevel_return(); /* re-program the PLL prior(!) starting the SDRAM controller */ - MPCTL0 = MPCTL0_VAL; - SPCTL0 = SPCTL0_VAL; - CSCR = CSCR_VAL | CSCR_UPDATE_DIS | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; + writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0); + writel(SPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_SPCTL0); + writel(CSCR_VAL | MX27_CSCR_UPDATE_DIS | MX27_CSCR_MPLL_RESTART | + MX27_CSCR_SPLL_RESTART, MX27_CCM_BASE_ADDR + MX27_CSCR); /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ - - DSCR(3) = 0x55555555; /* Set the driving strength */ - DSCR(5) = 0x55555555; - DSCR(6) = 0x55555555; - DSCR(7) = 0x00005005; - DSCR(8) = 0x15555555; - - writel(0x00000004, ESDMISC); /* Initial reset */ - writel(0x006ac73a, ESDCFG0); - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); for (i = 0; i < 8; i++) writel(0, 0xa0000f00); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, 0xa0000033); writeb(0xff, 0xa1000000); writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c index 58b1ec9ef4..715d604726 100644 --- a/arch/arm/boards/pcm038/pcm038.c +++ b/arch/arm/boards/pcm038/pcm038.c @@ -18,7 +18,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <fec.h> #include <notifier.h> #include <mach/gpio.h> @@ -39,6 +39,7 @@ #include <mach/devices-imx27.h> #include <mach/iim.h> #include <mfd/mc13xxx.h> +#include <mach/generic.h> #include "pll.h" @@ -111,8 +112,8 @@ static inline uint32_t get_pll_spctl10(void) { uint32_t reg; - reg = SPCTL0; - SPCTL0 = reg; + reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0); + writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0); return reg; } @@ -126,7 +127,8 @@ static int pcm038_power_init(void) struct mc13xxx *mc13xxx = mc13xxx_get(); /* PLL registers already set to their final values? */ - if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { + if (spctl0 == SPCTL0_VAL && + readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { console_flush(); if (mc13xxx) { mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), @@ -161,9 +163,9 @@ static int pcm038_power_init(void) /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); - CSCR = CSCR_VAL_FINAL; - PCDR0 = 0x130410c3; - PCDR1 = 0x09030911; + writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); + writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); + writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); @@ -173,7 +175,7 @@ static int pcm038_power_init(void) } /* clock gating enable */ - GPCR = 0x00050f08; + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); return 0; } @@ -281,9 +283,6 @@ static int pcm038_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - PCCR0 |= PCCR0_CSPI1_EN; - PCCR1 |= PCCR1_PERCLK2_EN; - spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); imx27_add_spi0(&pcm038_spi_0_data); @@ -293,7 +292,6 @@ static int pcm038_devices_init(void) imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); - PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN; imx27_add_i2c0(NULL); imx27_add_i2c1(NULL); @@ -302,11 +300,8 @@ static int pcm038_devices_init(void) */ imx27_add_fec(&fec_info); - switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { - case GPCR_BOOT_8BIT_NAND_2k: - case GPCR_BOOT_16BIT_NAND_2k: - case GPCR_BOOT_16BIT_NAND_512: - case GPCR_BOOT_8BIT_NAND_512: + switch (imx_bootsource()) { + case bootsource_nand: devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index a6b6c83efa..93a183988a 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -16,7 +16,7 @@ #include <init.h> #include <sizes.h> #include <platform_ide.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <mach/iomux-mx27.h> #include <mach/weim.h> #include <mach/gpio.h> @@ -112,35 +112,38 @@ static void pcm970_ide_init(void) mdelay(10); /* Reset PCMCIA Status Change Register */ - writel(0x00000fff, PCMCIA_PSCR); + writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR); mdelay(10); /* Check PCMCIA Input Pins Register for Card Detect & Power */ - if ((readl(PCMCIA_PIPR) & ((1 << 8) | (3 << 3))) != (1 << 8)) { + if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) & + ((1 << 8) | (3 << 3))) != (1 << 8)) { printf("CompactFlash card not found. Driver not enabled.\n"); return; } /* Disable all interrupts */ - writel(0, PCMCIA_PER); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER); /* Disable all PCMCIA banks */ for (i = 0; i < 5; i++) - writel(0, PCMCIA_POR(i)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i)); /* Not use internal PCOE */ - writel(0, PCMCIA_PGCR); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR); /* Setup PCMCIA bank0 for Common memory mode */ - writel(0, PCMCIA_PBR(0)); - writel(0, PCMCIA_POFR(0)); - writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, PCMCIA_POR(0)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0)); + writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, + MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); /* Clear PCMCIA General Status Register */ - writel(0x0000001f, PCMCIA_PGSR); + writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR); /* Make PCMCIA bank0 valid */ - writel(readl(PCMCIA_POR(0)) | (1 << 29), PCMCIA_POR(0)); + writel(readl(MX27_PCMCIA_POR(0)) | (1 << 29), + MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); platform_device_register(&pcm970_ide_device); } @@ -162,7 +165,6 @@ static void pcm970_mmc_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - PCCR0 |= PCCR0_SDHC2_EN; imx27_add_mmc1(NULL); } diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h index a7da4a44e3..8bdb76d111 100644 --- a/arch/arm/boards/pcm038/pll.h +++ b/arch/arm/boards/pcm038/pll.h @@ -22,35 +22,35 @@ /* define the PLL setting we want to run the system */ /* main clock divider settings immediately after reset (at 1.25 V core supply) */ -#define CSCR_VAL (CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_SP_SEL | /* 26 MHz reference */ \ - CSCR_MCU_SEL | /* 26 MHz reference */ \ - CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ - CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ - CSCR_FPM_EN | \ - CSCR_SPEN | \ - CSCR_MPEN) +#define CSCR_VAL (MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ + MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ + MX27_CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ + MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + MX27_CSCR_FPM_EN | \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN) /* main clock divider settings after core voltage increases to 1.45 V */ -#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_SP_SEL | /* 26 MHz reference */ \ - CSCR_MCU_SEL | /* 26 MHz reference */ \ - CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ - CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ - CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ - CSCR_FPM_EN | /* do not disable it! */ \ - CSCR_SPEN | \ - CSCR_MPEN) +#define CSCR_VAL_FINAL (MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ + MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ + MX27_CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ + MX27_CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ + MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + MX27_CSCR_FPM_EN | /* do not disable it! */ \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN) /* MPLL should provide a 399 MHz clock from the 26 MHz reference */ #define MPCTL0_VAL (IMX_PLL_PD(0) | \ diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index 6bd6508862..06f05abef1 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/cache-l2x0.h> @@ -65,6 +65,7 @@ void __bare_init __naked reset(void) uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; + unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; int i; @@ -109,28 +110,28 @@ void __bare_init __naked reset(void) * End of ARM1136 init */ - writel(0x003F4208, ccm_base + CCM_CCMR); + writel(0x003F4208, ccm_base + MX35_CCM_CCMR); /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); + writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); /* Check silicon revision and use 532MHz if >=2.1 */ r = readl(MX35_IIM_BASE_ADDR + 0x24); if (r >= IMX35_CHIP_REVISION_2_1) - writel(CCM_PDR0_532, ccm_base + CCM_PDR0); + writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0); else - writel(CCM_PDR0_399, ccm_base + CCM_PDR0); + writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); - r = readl(ccm_base + CCM_CGR0); + r = readl(ccm_base + MX35_CCM_CGR0); r |= 0x00300000; - writel(r, ccm_base + CCM_CGR0); + writel(r, ccm_base + MX35_CCM_CGR0); - r = readl(ccm_base + CCM_CGR1); + r = readl(ccm_base + MX35_CCM_CGR1); r |= 0x00000C00; r |= 0x00000003; - writel(r, ccm_base + CCM_CGR1); + writel(r, ccm_base + MX35_CCM_CGR1); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; @@ -153,17 +154,17 @@ void __bare_init __naked reset(void) writel(r, iomuxc_base + 0x7a4); /* MDDR init, enable mDDR*/ - writel(0x00000304, ESDMISC); /* was 0x00000004 */ + writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */ /* set timing paramters */ - writel(0x0025541F, ESDCFG0); + writel(0x0025541F, esdctl_base + IMX_ESDCFG0); /* select Precharge-All mode */ - writel(0x92220000, ESDCTL0); + writel(0x92220000, esdctl_base + IMX_ESDCTL0); /* Precharge-All */ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Load-Mode-Register mode */ - writel(0xB8001000, ESDCTL0); + writel(0xB8001000, esdctl_base + IMX_ESDCTL0); /* Load reg EMR2 */ writeb(0xda, 0x84000000); /* Load reg EMR3 */ @@ -174,18 +175,18 @@ void __bare_init __naked reset(void) writeb(0xda, 0x80000333); /* select Precharge-All mode */ - writel(0x92220000, ESDCTL0); + writel(0x92220000, esdctl_base + IMX_ESDCTL0); /* Precharge-All */ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Manual-Refresh mode */ - writel(0xA2220000, ESDCTL0); + writel(0xA2220000, esdctl_base + IMX_ESDCTL0); /* Manual-Refresh 2 times */ writel(0x87654321, MX35_CSD0_BASE_ADDR); writel(0x87654321, MX35_CSD0_BASE_ADDR); /* select Load-Mode-Register mode */ - writel(0xB2220000, ESDCTL0); + writel(0xB2220000, esdctl_base + IMX_ESDCTL0); /* Load reg MR -- CL3, BL8, end DLL reset */ writeb(0xda, 0x80000233); /* Load reg EMR1 -- OCD default */ @@ -197,12 +198,12 @@ void __bare_init __naked reset(void) * DSIZ32-bit, BL8, COL10-bit, ROW13-bit * disable PWT & PRCT * disable Auto-Refresh */ - writel(0x82220080, ESDCTL0); + writel(0x82220080, esdctl_base + IMX_ESDCTL0); /* enable Auto-Refresh */ - writel(0x82228080, ESDCTL0); + writel(0x82228080, esdctl_base + IMX_ESDCTL0); /* enable Auto-Refresh */ - writel(0x00002000, ESDCTL1); + writel(0x00002000, esdctl_base + IMX_ESDCTL1); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c index 09bc96af78..abfeaf148a 100644 --- a/arch/arm/boards/pcm043/pcm043.c +++ b/arch/arm/boards/pcm043/pcm043.c @@ -26,7 +26,7 @@ #include <environment.h> #include <fs.h> #include <sizes.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <asm/armlinux.h> #include <mach/gpio.h> #include <io.h> @@ -127,7 +127,7 @@ static int imx35_devices_init(void) led_gpio_register(&led0); - reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -308,10 +308,10 @@ static int do_cpufreq(int argc, char *argv[]) switch (freq) { case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S index 3c36889e7a..8f0000f822 100644 --- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S +++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S @@ -5,7 +5,7 @@ */ #include <config.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <mach/imx-pll.h> #include <asm/barebox-arm-head.h> @@ -21,20 +21,26 @@ /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */ - - writel(0x55555555, DSCR(3)) /* Set the driving strength */ - writel(0x55555555, DSCR(5)) - writel(0x55555555, DSCR(6)) - writel(0x00005005, DSCR(7)) - writel(0x15555555, DSCR(8)) - - writel(0x00000004, ESDMISC) /* Initial reset */ - writel(0x006ac73a, ESDCFG0) - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0) + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xa0000f00 mov r1, #0 @@ -44,14 +50,17 @@ subs r2, #1 bne 1b - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xA0000033 mov r1, #0xda strb r1, [r0] ldr r0, =0xA1000000 mov r1, #0xff strb r1, [r0] - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) .endm .section ".text_bare_init","ax" @@ -61,10 +70,10 @@ reset: common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 @@ -75,21 +84,26 @@ reset: b board_init_lowlevel_return 1: + /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ - - writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL | - CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN | - CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) | - CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL | - CSCR_MSHC_SEL, CSCR) + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) + + writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | + MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | + MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | + MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | + MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | + MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | + MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | + MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR) sdram_init diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c index 45e59fbfd2..0b66b04e5f 100644 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -18,7 +18,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx-regs.h> +#include <mach/imx27-regs.h> #include <fec.h> #include <mach/gpio.h> #include <asm/armlinux.h> @@ -279,8 +279,6 @@ static int pca100_devices_init(void) PD18_PF_I2C_CLK, }; - PCCR0 |= PCCR0_SDHC2_EN; - pca100_usb_init(); /* initizalize gpios */ @@ -292,8 +290,6 @@ static int pca100_devices_init(void) imx27_add_mmc1(NULL); imx27_add_fb(&pca100_fb_data); - PCCR1 |= PCCR1_PERCLK2_EN; - #ifdef CONFIG_USB pca100_usb_register(); #endif diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index fabc89ea1e..cefac8481a 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -#include <mach/imx-regs.h> +#include <mach/imx1-regs.h> #include <asm/barebox-arm-head.h> #define CPU200 @@ -82,13 +82,13 @@ reset: common_reset r0 /* Change PERCLK1DIV to 14 ie 14+1 */ - writel(CFG_PCDR_VAL, PCDR) + writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR) /* set MCU PLL Control Register 0 */ - writel(CFG_MPCTL0_VAL, MPCTL0) + writel(CFG_MPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_MPCTL0) /* set mpll restart bit */ - ldr r0, =CSCR + ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR ldr r1, [r0] orr r1,r1,#(1<<21) str r1, [r0] @@ -104,10 +104,10 @@ reset: bne 1b /* set System PLL Control Register 0 */ - writel(CFG_SPCTL0_VAL, SPCTL0) + writel(CFG_SPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_SPCTL0) /* set spll restart bit */ - ldr r0, =CSCR + ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR ldr r1, [r0] orr r1,r1,#(1<<22) str r1, [r0] @@ -122,7 +122,7 @@ reset: subs r2,r2,#1 bne 1b - writel(CFG_CSCR_VAL, CSCR) + writel(CFG_CSCR_VAL, MX1_CCM_BASE_ADDR + MX1_CSCR) /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon *this..... @@ -157,9 +157,12 @@ reset: /* SDRAM Setup */ - writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */ - writel(0x0, 0x08200000) /* Issue Precharge all Command */ - writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */ + /* Precharge cmd, CAS = 2 */ + writel(0x910a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) + /* Issue Precharge all Command */ + writel(0x0, 0x08200000) + /* Autorefresh cmd, CAS = 2 */ + writel(0xa10a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) ldr r0, =0x08000000 ldr r1, =0x0 /* Issue AutoRefresh Command */ @@ -172,8 +175,10 @@ reset: str r1, [r0] str r1, [r0] - writel(0xb10a8300, SDCTL0) - writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ - writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */ + writel(0xb10a8300, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) + /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ + writel(0x0, 0x08223000) + /* Set to Normal Mode CAS 2 */ + writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) b board_init_lowlevel_return diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index c83132adc8..c70852c308 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -19,7 +19,7 @@ #include <init.h> #include <environment.h> #include <generated/mach-types.h> -#include <mach/imx-regs.h> +#include <mach/imx1-regs.h> #include <asm/armlinux.h> #include <mach/gpio.h> #include <mach/weim.h> @@ -29,6 +29,7 @@ #include <fcntl.h> #include <dm9000.h> #include <led.h> +#include <mach/iomux-mx1.h> #include <mach/devices-imx1.h> static struct dm9000_platform_data dm9000_data = { @@ -68,8 +69,8 @@ static int scb9328_devices_init(void) for (i = 0; i < ARRAY_SIZE(leds); i++) led_gpio_register(&leds[i]); -/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ - FMCR = 0x1; + /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ + writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR); imx1_setup_eimcs(0, 0x000F2000, 0x11110d01); imx1_setup_eimcs(1, 0x000F0a00, 0x11110601); diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c index 8c3d855608..77535b53f2 100644 --- a/arch/arm/boards/tqma53/board.c +++ b/arch/arm/boards/tqma53/board.c @@ -30,7 +30,7 @@ #include <asm/mmu.h> #include <generated/mach-types.h> -#include <mach/imx-regs.h> +#include <mach/imx53-regs.h> #include <mach/iomux-mx53.h> #include <mach/devices-imx53.h> #include <mach/generic.h> |