path: root/arch/arm/cpu/mmu.c
diff options
authorSascha Hauer <>2018-08-15 15:39:22 +0200
committerSascha Hauer <>2018-08-21 09:14:43 +0200
commit12907adf6616f4d753ef0d9db3a9aa0bb08567d8 (patch)
tree950174bc52748bbe082f06a7b85d2d9d69e20e84 /arch/arm/cpu/mmu.c
parente20a6877664d23c22a7291ade961a993b18f1bf0 (diff)
ARM: MMU: fix wrong dma_flush_range in arm_create_pte()
Since 7ba0f2d299 arm_create_pte() flushes the page table entries itself and it's no longer done in arch_remap_range(). Unfortunately it does not flush the modified 1st level page table entry, but instead the base of the page table. Fix it up. Fixes: 7ba0f2d299 ARM: mmu: fix cache flushing when replacing a section with a PTE Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'arch/arm/cpu/mmu.c')
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 88ee11c..f6c44e3 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -151,7 +151,7 @@ static u32 *arm_create_pte(unsigned long virt, uint32_t flags)
dma_flush_range(table, PTRS_PER_PTE * sizeof(u32));
ttb[ttb_idx] = (unsigned long)table | PMD_TYPE_TABLE;
- dma_flush_range(ttb, sizeof(u32));
+ dma_flush_range(&ttb[ttb_idx], sizeof(u32));
return table;