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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-05-21 20:15:09 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-05-22 09:13:55 +0200 |
| commit | ee9576d2679537a292b8f5e50765eba707be7c87 (patch) | |
| tree | e8ebafe2bbd3506bb04b57b40df10cc0b8440272 /arch/arm/cpu/mmu.c | |
| parent | e3e54c64418076e27b941c2450ef718a377e57da (diff) | |
| download | barebox-ee9576d2679537a292b8f5e50765eba707be7c87.tar.gz barebox-ee9576d2679537a292b8f5e50765eba707be7c87.tar.xz | |
ARM: mmu: Introduce ARM_TTB_SIZE
Commit 1c33aacf8a247ab45814b43ac0ca903677afffae ("ARM: use memalign to
allocate page table"), reasonalby changed TTB allocation size from
SZ_32K to SZ_16K (TTB's real size), but it also changed alignment from
SZ_16K to SZ_64K for unclear reasons.
Reading various TTBR related ARM documentation it seems that worst
case alignment for it is 16KiB (bits [0, 13 - N] must be zero) which
also matches early TTB allocation code.
Since both early and regular MMU code has to share this paramter,
introduce ARM_TTB_SIZE and use it in both cases for both size and
alignment.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/mmu.c')
| -rw-r--r-- | arch/arm/cpu/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 5f82b63cad..a89f420f20 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -469,7 +469,7 @@ static int mmu_init(void) pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n", ttb); } else { - ttb = xmemalign(0x10000, 0x4000); + ttb = xmemalign(ARM_TTB_SIZE, ARM_TTB_SIZE); } pr_debug("ttb: 0x%p\n", ttb); |