ARM: l2x0: Flush cache before disabling it

Otherwise entries may still be in the cache and never reach memory.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 15 insertions, 3 deletions

diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 6d6e044cf1..665f86277c 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -113,6 +113,13 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 }
 
+static void l2x0_flush_all(void)
+{
+	writel(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+	cache_wait(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
+	cache_sync();
+}
+
 static void l2x0_disable(void)
 {
 	writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
@@ -178,5 +185,9 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
 	outer_cache.disable = l2x0_disable;
-}
+	outer_cache.flush_all = l2x0_flush_all;
 
+	pr_debug("%s cache controller enabled\n", type);
+	pr_debug("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
+			ways, cache_id, aux);
+}
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 7b161d59d6..27ead1c177 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -71,6 +71,8 @@ void __mmu_cache_flush(void)
 {
 	if (cache_fns)
 		cache_fns->mmu_cache_flush();
+	if (outer_cache.flush_all)
+		outer_cache.flush_all();
 }
 
 int arm_set_cache_functions(void)
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 5e708023e4..ff8f43d175 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -79,10 +79,9 @@ struct outer_cache_fns outer_cache;
  */
 void mmu_disable(void)
 {
+	__mmu_cache_flush();
 	if (outer_cache.disable)
 		outer_cache.disable();
-
-	__mmu_cache_flush();
 	__mmu_cache_off();
 }