summaryrefslogtreecommitdiffstats
path: root/arch/arm/cpu
diff options
context:
space:
mode:
authorAlexander Kurz <akurz@blala.de>2016-03-02 23:51:28 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2016-03-04 07:58:48 +0100
commit7fb798c2d3c0e0b20cae55bdfacfafe7e12e8f4f (patch)
treed4804c80f09e56ea5bd8676ac40711f338b77639 /arch/arm/cpu
parent4189af5812ad95a485490917b5bce671f57f79c2 (diff)
downloadbarebox-7fb798c2d3c0e0b20cae55bdfacfafe7e12e8f4f.tar.gz
barebox-7fb798c2d3c0e0b20cae55bdfacfafe7e12e8f4f.tar.xz
arm/cpu/lowlevel: fix: possible processor mode change
This is a re-application of fix 17644b55. arm_cpu_lowlevel_init() will set the processor mode to 0x13 (supervisor). When this function is entered via a different processor mode, register banking will happen to lr (r14), resulting in an invalid return address. This fix will preserve the return address manually. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/lowlevel.S4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index b76222d8f3..e5baa12346 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -4,6 +4,8 @@
.section ".text_bare_init_","ax"
ENTRY(arm_cpu_lowlevel_init)
+ /* save lr, since it may be banked away with a processor mode change */
+ mov r2, lr
/* set the cpu to SVC32 mode, mask irq and fiq */
mrs r12, cpsr
bic r12, r12, #0x1f
@@ -54,5 +56,5 @@ ENTRY(arm_cpu_lowlevel_init)
mcr p15, 0, r12, c1, c0, 0 /* SCTLR */
- mov pc, lr
+ mov pc, r2
ENDPROC(arm_cpu_lowlevel_init)