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authorRaphael Poggi <poggi.raph@gmail.com>2016-07-04 13:52:52 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-07-06 11:23:49 +0200
commitada79ea0790fa3a7d311a985eea0eb168cb829c5 (patch)
treecaf6dab56365928de8e2ca32844eb77c9b3dc206 /arch/arm/cpu
parent9159f08ae7578a5b49568ca808730b3cae14b0a8 (diff)
downloadbarebox-ada79ea0790fa3a7d311a985eea0eb168cb829c5.tar.gz
barebox-ada79ea0790fa3a7d311a985eea0eb168cb829c5.tar.xz
arm: cpu: disable code portion in armv8 case
Enclosed by #if directive OMAP specific code and mmu_disable (ARMv8 code will implemented it somewhere else). Signed-off-by: Raphael Poggi <poggi.raph@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/cpu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index eb12166c16..cc54324c29 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -68,6 +68,7 @@ int icache_status(void)
return (get_cr () & CR_I) != 0;
}
+#if __LINUX_ARM_ARCH__ <= 7
/*
* SoC like the ux500 have the l2x0 always enable
* with or without MMU enable
@@ -86,6 +87,7 @@ void mmu_disable(void)
}
__mmu_cache_off();
}
+#endif
/**
* Disable MMU and D-cache, flush caches
@@ -100,6 +102,8 @@ static void arch_shutdown(void)
mmu_disable();
flush_icache();
+
+#if __LINUX_ARM_ARCH__ <= 7
/*
* barebox normally does not use interrupts, but some functionalities
* (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
@@ -108,6 +112,7 @@ static void arch_shutdown(void)
__asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
r |= PSR_I_BIT;
__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+#endif
}
archshutdown_exitcall(arch_shutdown);