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authorSascha Hauer <s.hauer@pengutronix.de>2020-02-18 15:48:26 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-02-19 09:20:03 +0100
commit07199cefe060aed82febc8a88ee8f80b37444456 (patch)
tree33d0ef85e46030ac70fa83a765668764e988b8b4 /arch/arm/cpu
parent2eb5ed5b57e1a60768293912be980e006e834253 (diff)
downloadbarebox-07199cefe060aed82febc8a88ee8f80b37444456.tar.gz
barebox-07199cefe060aed82febc8a88ee8f80b37444456.tar.xz
ARM: i.MX: external NAND boot: Leave icache disabled
It seems running from the NFC SRAM doesn't work with the instruction cache enabled, it leads to corruptions on the i.MX27. We stumbled upon this earlier and the solution at that time was to disable the instruction cache in the NAND boot code. It is, however, more reliable to just not enable the instruction cache in the first place. This is not particularly nice as we have to ifdef this in generic code, duplicate arm_cpu_lowlevel_init(), or call arm_cpu_lowlevel_init() later when we are out of NFC SRAM. From the different bad solutions I chose to ifdef the instruction cache away. It will be enabled later in the common cache functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/lowlevel.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 3b52644e43..203a4afc47 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -57,8 +57,10 @@ THUMB( orr r12, r12, #PSR_T_BIT )
bic r12, r12, #(CR_M | CR_C | CR_B)
bic r12, r12, #(CR_S | CR_R | CR_V)
+#ifndef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
/* enable instruction cache */
orr r12, r12, #CR_I
+#endif
#if __LINUX_ARM_ARCH__ >= 6
orr r12, r12, #CR_U