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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2019-12-19 10:13:10 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-12-20 16:14:20 +0100 |
| commit | a4c192afe05376a9423608e93fb5c5b56f2c4fd0 (patch) | |
| tree | 9e43eb705b487e27fc7682d7a2a78e05a256cf06 /arch/arm/cpu | |
| parent | 3f26f8ca7038a8f5d817b19b25ad8045a4eb4d1a (diff) | |
| download | barebox-a4c192afe05376a9423608e93fb5c5b56f2c4fd0.tar.gz barebox-a4c192afe05376a9423608e93fb5c5b56f2c4fd0.tar.xz | |
ARM: cache_64: invalidate icache in arm_early_mmu_cache_flush
So far arm_early_mmu_cache_flush has only been used in preparation for
executing newly-written code. For this reason, on ARMv7 and below,
it had always invalidate the icache after the dcache flush.
We don't do this on ARM64, but sync_caches_for_execution depends on this,
which had this comment that didn't hold true for ARM64:
> Despite the name arm_early_mmu_cache_flush not only flushes the
> data cache, but also invalidates the instruction cache.
It might be worthwhile to decouple dcache flushing from icache
invalidation, but for now, align what we do on ARM64 with what we do for
32-bit ARMs.
This fixes a potential read of stale instructions when loading
second-stage barebox from the PBL with MMU disabled.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/cache_64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/cache_64.c b/arch/arm/cpu/cache_64.c index 81c37e1c34..6e18d981a4 100644 --- a/arch/arm/cpu/cache_64.c +++ b/arch/arm/cpu/cache_64.c @@ -27,6 +27,7 @@ int arm_set_cache_functions(void) void arm_early_mmu_cache_flush(void) { v8_flush_dcache_all(); + v8_invalidate_icache_all(); } void arm_early_mmu_cache_invalidate(void) |