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author | Ahmad Fatoum <ahmad@a3f.at> | 2019-10-09 18:40:07 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-14 15:26:46 +0200 |
commit | ae0a375ba71ba9b9a70cb7eda177445fcfbf586d (patch) | |
tree | 65ba5914c10073d826b937b01ee5be16d8dc0883 /arch/arm/cpu | |
parent | 843b24bf6d569647f85f69942e3db1940a54f26c (diff) | |
download | barebox-ae0a375ba71ba9b9a70cb7eda177445fcfbf586d.tar.gz barebox-ae0a375ba71ba9b9a70cb7eda177445fcfbf586d.tar.xz |
ARM: cache-armv7: remove duplicate domain initialization
We already call set_domain each time we do __mmu_cache_on. Writing the
DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it.
This changes existing behavior, whereas all 16 memory domains had the same
access permissions set (manager) before, now only the first domain has.
This is ok, as we only ever use domain 0 in barebox and on non-armv7,
we don't bother with the other ones at all.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/cache-armv7.S | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 43ec902133..0f6108426c 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -20,8 +20,6 @@ ENTRY(v7_mmu_cache_on) orr r0, r0, #1 << 25 @ big-endian page tables #endif orrne r0, r0, #1 @ MMU enabled - movne r1, #-1 - mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif isb mcr p15, 0, r0, c1, c0, 0 @ load control register |