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authorSascha Hauer <s.hauer@pengutronix.de>2021-06-21 11:27:58 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2021-06-24 08:55:41 +0200
commitbaf57b8e8df1b7303f5bd0aaaa47a3eed4284439 (patch)
tree2b718e55ce124cacd547029ecb90e1b82a2ceac6 /arch/arm/cpu
parente024dbb75174330bef2a4ae62faace649da80abd (diff)
downloadbarebox-baf57b8e8df1b7303f5bd0aaaa47a3eed4284439.tar.gz
barebox-baf57b8e8df1b7303f5bd0aaaa47a3eed4284439.tar.xz
ARM: Add atf common support
ARM trusted firmware has some common data structures passed to bl31. This patch imports the code supporting this taken from U-Boot. The defines and data structures are taken directly from U-Boot, the support code is heavily modified for the sake of readability. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210615141641.31577-9-s.hauer@pengutronix.de Link: https://lore.barebox.org/20210621092802.27275-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/Makefile1
-rw-r--r--arch/arm/cpu/atf.c80
2 files changed, 81 insertions, 0 deletions
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index e7a6e3e6fb..6344ab5066 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -50,6 +50,7 @@ AFLAGS-cache-armv8.pbl.o :=-Wa,-march=armv8-a
pbl-y += entry.o entry_ll$(S64).o
pbl-y += uncompress.o
+pbl-$(CONFIG_ARM_ATF) += atf.o
obj-pbl-y += common.o sections.o
KASAN_SANITIZE_common.o := n
diff --git a/arch/arm/cpu/atf.c b/arch/arm/cpu/atf.c
new file mode 100644
index 0000000000..4753a8a559
--- /dev/null
+++ b/arch/arm/cpu/atf.c
@@ -0,0 +1,80 @@
+#include <common.h>
+#include <asm/atf_common.h>
+#include <asm/system.h>
+
+static inline void raw_write_daif(unsigned int daif)
+{
+ __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
+}
+
+void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
+ uintptr_t bl33_entry, uintptr_t fdt_addr)
+{
+ struct atf_image_info bl31_image_info = {
+ .h = {
+ .type = ATF_PARAM_IMAGE_BINARY,
+ .version = ATF_VERSION_1,
+ .size = sizeof(bl31_image_info),
+ },
+ };
+ struct atf_image_info bl32_image_info = {
+ .h = {
+ .type = ATF_PARAM_IMAGE_BINARY,
+ .version = ATF_VERSION_1,
+ .size = sizeof(bl32_image_info),
+ },
+ };
+ struct entry_point_info bl32_ep_info = {
+ .h = {
+ .type = ATF_PARAM_EP,
+ .version = ATF_VERSION_1,
+ .attr = ATF_EP_SECURE,
+ .size = sizeof(bl32_ep_info),
+ },
+ .pc = bl32_entry,
+ .spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+ .args = {
+ .arg3 = fdt_addr,
+ },
+ };
+ struct atf_image_info bl33_image_info = {
+ .h = {
+ .type = ATF_PARAM_IMAGE_BINARY,
+ .version = ATF_VERSION_1,
+ .size = sizeof(bl33_image_info),
+ },
+ };
+ struct entry_point_info bl33_ep_info = {
+ .h = {
+ .type = ATF_PARAM_EP,
+ .version = ATF_VERSION_1,
+ .attr = ATF_EP_NON_SECURE,
+ .size = sizeof(bl33_ep_info),
+ },
+ .pc = bl33_entry,
+ .spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXECPTIONS),
+ .args = {
+ /* BL33 expects to receive the primary CPU MPID (through x0) */
+ .arg0 = 0xffff & read_mpidr(),
+ },
+ };
+ struct bl31_params bl31_params = {
+ .h = {
+ .type = ATF_PARAM_BL31,
+ .version = ATF_VERSION_1,
+ .size = sizeof(bl31_params),
+ },
+ .bl31_image_info = &bl31_image_info,
+ .bl32_ep_info = &bl32_ep_info,
+ .bl32_image_info = &bl32_image_info,
+ .bl33_ep_info = &bl33_ep_info,
+ .bl33_image_info = &bl33_image_info,
+ };
+ void (*atf_entry)(struct bl31_params *params, uintptr_t plat_params);
+
+ raw_write_daif(SPSR_EXCEPTION_MASK);
+
+ atf_entry = (void *)bl31_entry;
+
+ atf_entry(&bl31_params, fdt_addr);
+}