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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-05-13 12:26:05 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-05-13 12:37:42 +0200 |
commit | c5c08624f73a0b7e8f822127b256b19ff1b6f553 (patch) | |
tree | 9e5bcb34a67a3be99affbef2efac404bcc4a974a /arch/arm/cpu | |
parent | b0a89d8086577ee0b8d9eb81d7fdd07e8f7662dd (diff) | |
download | barebox-c5c08624f73a0b7e8f822127b256b19ff1b6f553.tar.gz barebox-c5c08624f73a0b7e8f822127b256b19ff1b6f553.tar.xz |
ARM: introduce sync_caches_for_execution
We have several places in the code which which prepares just modified code
for execution. This is done differently in all the places, so add a common
function to be used by all.
Most places called arm_early_mmu_cache_flush(). This function includes
invalidating the instruction cache, so doing it again is unnecessary.
Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU.
The ifdef seems unnecessary since we do not have it consistently, so
remove the ifdef.
Some early i.MX xload code had icache_invalidate() but forgot to flush
the caches. Replace the instruction cache invalidation with
sync_caches_for_execution().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/common.c | 19 | ||||
-rw-r--r-- | arch/arm/cpu/setupc.S | 12 | ||||
-rw-r--r-- | arch/arm/cpu/setupc_64.S | 5 | ||||
-rw-r--r-- | arch/arm/cpu/start-pbl.c | 3 | ||||
-rw-r--r-- | arch/arm/cpu/uncompress.c | 3 |
5 files changed, 23 insertions, 19 deletions
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c index 51fe7ed988..821cafbf26 100644 --- a/arch/arm/cpu/common.c +++ b/arch/arm/cpu/common.c @@ -27,6 +27,22 @@ #include <asm/cache.h> #include <debug_ll.h> +/** + * sync_caches_for_execution - synchronize caches for code execution + * + * Code has been modified in memory, call this before executing it. + * This function flushes the data cache up to the point of unification + * and invalidates the instruction cache. + */ +void sync_caches_for_execution(void) +{ + /* + * Despite the name arm_early_mmu_cache_flush not only flushes the + * data cache, but also invalidates the instruction cache. + */ + arm_early_mmu_cache_flush(); +} + #define R_ARM_RELATIVE 23 #define R_AARCH64_RELATIVE 1027 @@ -103,8 +119,7 @@ void relocate_to_current_adr(void) #error "Architecture not specified" #endif - arm_early_mmu_cache_flush(); - icache_invalidate(); + sync_caches_for_execution(); } #ifdef ARM_MULTIARCH diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc.S index a5f311b8ec..8ae7c89a2c 100644 --- a/arch/arm/cpu/setupc.S +++ b/arch/arm/cpu/setupc.S @@ -27,11 +27,7 @@ ENTRY(setup_c) ldr r2, =__bss_stop sub r2, r2, r0 bl memset /* clear bss */ -#ifdef CONFIG_MMU - bl arm_early_mmu_cache_flush -#endif - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* flush icache */ + bl sync_caches_for_execution sub lr, r5, r4 /* adjust return address to new location */ pop {r4, r5} mov pc, lr @@ -73,11 +69,7 @@ ENTRY(relocate_to_adr) bl memcpy /* copy binary */ -#ifdef CONFIG_MMU - bl arm_early_mmu_cache_flush -#endif - mov r0,#0 - mcr p15, 0, r0, c7, c5, 0 /* flush icache */ + bl sync_caches_for_execution ldr r0,=1f sub r0, r0, r8 diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S index 61e70850d7..ee9ea6cfc0 100644 --- a/arch/arm/cpu/setupc_64.S +++ b/arch/arm/cpu/setupc_64.S @@ -56,9 +56,8 @@ ENTRY(relocate_to_adr) bl memcpy /* copy binary */ -#ifdef CONFIG_MMU - bl arm_early_mmu_cache_flush -#endif + bl sync_caches_for_execution + mov x0,#0 ic ivau, x0 /* flush icache */ diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c index 25ef0d3d82..f5c7cfec19 100644 --- a/arch/arm/cpu/start-pbl.c +++ b/arch/arm/cpu/start-pbl.c @@ -95,8 +95,7 @@ __noreturn void barebox_single_pbl_start(unsigned long membase, pbl_barebox_uncompress((void*)barebox_base, (void *)pg_start, pg_len); - arm_early_mmu_cache_flush(); - icache_invalidate(); + sync_caches_for_execution(); if (IS_ENABLED(CONFIG_THUMB2_BAREBOX)) barebox = (void *)(barebox_base + 1); diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index e52716557b..c7851c5c75 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -94,8 +94,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase, pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len); - arm_early_mmu_cache_flush(); - icache_invalidate(); + sync_caches_for_execution(); if (IS_ENABLED(CONFIG_THUMB2_BAREBOX)) barebox = (void *)(barebox_base + 1); |