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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-06-18 13:51:22 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-07-11 09:53:16 +0200 |
| commit | 1ee484f3829e3f69d43fa46aa210a12ffc610908 (patch) | |
| tree | 4fb466ee1660fa7268611777a0228561ab68c902 /arch/arm/dts/imx6q-tqma6q.dtsi | |
| parent | 24bd4d0d6fc61eb434b1cd785d349e01c7d6c1a3 (diff) | |
| download | barebox-1ee484f3829e3f69d43fa46aa210a12ffc610908.tar.gz barebox-1ee484f3829e3f69d43fa46aa210a12ffc610908.tar.xz | |
ARM: i.MX6: TQ tqma6x initial board support
The TQ tqma6x comes in two different variants. One i.MX6s based
tqma6s and a i.MX6q based tqma6q.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/dts/imx6q-tqma6q.dtsi')
| -rw-r--r-- | arch/arm/dts/imx6q-tqma6q.dtsi | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6q-tqma6q.dtsi b/arch/arm/dts/imx6q-tqma6q.dtsi new file mode 100644 index 0000000000..882f409089 --- /dev/null +++ b/arch/arm/dts/imx6q-tqma6q.dtsi @@ -0,0 +1,132 @@ +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6x.dtsi" + +&iomuxc { + can1 { + pinctrl_can1_1: can1grp-1 { + fsl,pins = < + MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + >; + }; + }; + + can2 { + pinctrl_can2_1: can2grp-1 { + fsl,pins = < + MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + }; + + disp0 { + pinctrl_disp0_ipu1: disp0grp-1 { + fsl,pins = < + MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000 + MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000 + MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000 + MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000 + MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000 + MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000 + MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000 + MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000 + MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000 + MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000 + MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000 + MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000 + MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000 + MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000 + MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000 + MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000 + MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000 + MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000 + MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000 + MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000 + MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000 + MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000 + MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000 + MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000 + MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000 + MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000 + MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000 + MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000 + >; + }; + + pinctrl_disp0_ipu2: disp0grp-2 { + fsl,pins = < + MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x80000000 + MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x80000000 + MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x80000000 + MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x80000000 + MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x80000000 + MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x80000000 + MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x80000000 + MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x80000000 + MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x80000000 + MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x80000000 + MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x80000000 + MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x80000000 + MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x80000000 + MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x80000000 + MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x80000000 + MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x80000000 + MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x80000000 + MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x80000000 + MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x80000000 + MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x80000000 + MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x80000000 + MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x80000000 + MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x80000000 + MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x80000000 + MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x80000000 + MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x80000000 + MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x80000000 + MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x80000000 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6Q_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_tqma6x: usdhc2grp-tqma6x { + fsl,pins = < + MX6Q_PAD_SD2_CMD__SD2_CMD 0x000070f0 + MX6Q_PAD_SD2_CLK__SD2_CLK 0x000070f0 + MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x000070f0 + MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x000070f0 + MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x000070f0 + MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x000070f0 + >; + }; + }; +}; |