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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-05-09 10:01:10 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-05-19 08:37:19 +0200 |
| commit | a5207a633a054adbd3cbf104436492f0bc57b104 (patch) | |
| tree | f18feba1597b80f64327e3e7f87dc4273b0a9a2e /arch/arm/dts/imx6q-var-custom.dts | |
| parent | eeb3cd13691b913cd9176a46a658eb2b1413b6a5 (diff) | |
| download | barebox-a5207a633a054adbd3cbf104436492f0bc57b104.tar.gz barebox-a5207a633a054adbd3cbf104436492f0bc57b104.tar.xz | |
ARM: dts: i.MX6: drop usage of pin group defines
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/dts/imx6q-var-custom.dts')
| -rw-r--r-- | arch/arm/dts/imx6q-var-custom.dts | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/arch/arm/dts/imx6q-var-custom.dts b/arch/arm/dts/imx6q-var-custom.dts index bb1193f9a4..795114d841 100644 --- a/arch/arm/dts/imx6q-var-custom.dts +++ b/arch/arm/dts/imx6q-var-custom.dts @@ -42,26 +42,42 @@ imx6q-variscite-custom { pinctrl_i2c1: i2c1grp { - fsl,pins = <MX6QDL_I2C1_PINGRP1>; + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; }; pinctrl_i2c3: i2c3grp { - fsl,pins = <MX6QDL_I2C3_PINGRP3>; + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>; + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; }; pinctrl_usdhc2_cd: usdhc2cd { fsl,pins = < - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 >; }; pinctrl_uart1: uart1grp { - fsl,pins = <MX6QDL_UART1_PINGRP1>; + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; }; }; }; |