Merge branch 'for-next/rockchip'

2 files changed, 149 insertions, 0 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 09bf68ea2b..d1a3fe8ae8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
 pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
+pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
 pbl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
 pbl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
 pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
diff --git a/arch/arm/dts/rk3288-phycore-som.dts b/arch/arm/dts/rk3288-phycore-som.dts
new file mode 100644
index 0000000000..5410bd1f76
--- /dev/null
+++ b/arch/arm/dts/rk3288-phycore-som.dts
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH,
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <arm/rk3288.dtsi>
+
+/ {
+	model = "phycore-rk3288";
+	compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	vcc33: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc33";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc18: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+
+		environment-emmc {
+			compatible = "barebox,environment";
+			device-path = &emmc, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-sdmmc {
+			compatible = "barebox,environment";
+			device-path = &sdmmc, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
+
+&pinctrl {
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&emmc {
+	broken-cd;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+	vmmc-supply = <&vcc33>;
+	vqmmc-supply = <&vcc18>;
+	status = "okay";
+
+	#size-cells = <1>;
+	#address-cells = <1>;
+
+	partition@8000 {
+		label = "spl";
+		reg = <0x8000 0x8000>;
+	};
+
+	partition@20000 {
+		label = "barebox";
+		reg = <0x20000 0x80000>;
+	};
+
+	partition@a0000 {
+		label = "barebox-environment";
+		reg = <0xa0000 0x20000>;
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	vmmc-supply = <&vcc33>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@8000 {
+		label = "spl";
+		reg = <0x8000 0x8000>;
+	};
+
+	partition@20000 {
+		label = "barebox";
+		reg = <0x20000 0x80000>;
+	};
+
+	partition@a0000 {
+		label = "barebox-environment";
+		reg = <0xa0000 0x20000>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
+	reg-shift = <2>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};