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| author | Michael Riesch <michael.riesch@wolfvision.net> | 2022-05-09 13:36:17 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-05-11 08:28:05 +0200 |
| commit | 7edf73d4b46faf42e6a783f63cda2aeb34151d13 (patch) | |
| tree | b4a03c49d5cb2e33f25ef6d8d7e5f92e7bccbac5 /arch/arm/dts | |
| parent | f0bcb9b6f3e7cd278535ccb587d7c147efb5e79c (diff) | |
| download | barebox-7edf73d4b46faf42e6a783f63cda2aeb34151d13.tar.gz barebox-7edf73d4b46faf42e6a783f63cda2aeb34151d13.tar.xz | |
phy: rockchip: align naneng-combphy clocks and resets with binding
There was no device tree binding in mainline Linux when this driver
was introduced in barebox. This has changed in the mean time, hence
we need to align the clocks and resets in this driver.
This step is a prerequisite for replacing the initial rk3568.dtsi in
arch/arm/dts with the mainline Linux version. For compatibility, the
former is updated accordingly.
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.barebox.org/20220509113618.1602657-2-michael.riesch@wolfvision.net
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/rk3568.dtsi | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi index 0f19d3f0c0..28121dbdf3 100644 --- a/arch/arm/dts/rk3568.dtsi +++ b/arch/arm/dts/rk3568.dtsi @@ -367,11 +367,10 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; + clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; - reset-names = "combphy-apb", "combphy"; + resets = <&cru SRST_PIPEPHY0>; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf0>; status = "disabled"; @@ -383,11 +382,10 @@ #phy-cells = <1>; clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; + clock-names = "ref", "apb", "pipe"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; - reset-names = "combphy-apb", "combphy"; + resets = <&cru SRST_PIPEPHY1>; rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf1>; status = "disabled"; |