Merge branch 'for-next/vexpress'

3 files changed, 136 insertions, 0 deletions

diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index 0433279b82..8a58390a19 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -12,7 +12,12 @@
  *
  * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
  * can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
  */
+#define TIMER_1_BASE	0x00
+#define TIMER_2_BASE	0x20
+
 #define TIMER_LOAD	0x00			/* ACVR rw */
 #define TIMER_VALUE	0x04			/* ACVR ro */
 #define TIMER_CTRL	0x08			/* ACVR rw */
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
new file mode 100644
index 0000000000..3e3996a99e
--- /dev/null
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/include/asm/hardware/sp810.h
+ *
+ * ARM PrimeXsys System Controller SP810 header file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar <viresh.linux@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_SP810_H
+#define __ASM_ARM_SP810_H
+
+#include <io.h>
+
+/* sysctl registers offset */
+#define SCCTRL			0x000
+#define SCSYSSTAT		0x004
+#define SCIMCTRL		0x008
+#define SCIMSTAT		0x00C
+#define SCXTALCTRL		0x010
+#define SCPLLCTRL		0x014
+#define SCPLLFCTRL		0x018
+#define SCPERCTRL0		0x01C
+#define SCPERCTRL1		0x020
+#define SCPEREN			0x024
+#define SCPERDIS		0x028
+#define SCPERCLKEN		0x02C
+#define SCPERSTAT		0x030
+#define SCSYSID0		0xEE0
+#define SCSYSID1		0xEE4
+#define SCSYSID2		0xEE8
+#define SCSYSID3		0xEEC
+#define SCITCR			0xF00
+#define SCITIR0			0xF04
+#define SCITIR1			0xF08
+#define SCITOR			0xF0C
+#define SCCNTCTRL		0xF10
+#define SCCNTDATA		0xF14
+#define SCCNTSTEP		0xF18
+#define SCPERIPHID0		0xFE0
+#define SCPERIPHID1		0xFE4
+#define SCPERIPHID2		0xFE8
+#define SCPERIPHID3		0xFEC
+#define SCPCELLID0		0xFF0
+#define SCPCELLID1		0xFF4
+#define SCPCELLID2		0xFF8
+#define SCPCELLID3		0xFFC
+
+#define SCCTRL_TIMEREN0SEL_REFCLK	(0 << 15)
+#define SCCTRL_TIMEREN0SEL_TIMCLK	(1 << 15)
+
+#define SCCTRL_TIMEREN1SEL_REFCLK	(0 << 17)
+#define SCCTRL_TIMEREN1SEL_TIMCLK	(1 << 17)
+
+static inline void sysctl_soft_reset(void __iomem *base)
+{
+	/* switch to slow mode */
+	writel(0x2, base + SCCTRL);
+
+	/* writing any value to SCSYSSTAT reg will reset system */
+	writel(0, base + SCSYSSTAT);
+}
+
+#endif	/* __ASM_ARM_SP810_H */
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index 5b676313c0..56ebb11a2b 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARM_SYSTEM_INFO_H
 #define __ASM_ARM_SYSTEM_INFO_H
 
+#include <asm/cputype.h>
+
 #define CPU_ARCH_UNKNOWN	0
 #define CPU_ARCH_ARMv3		1
 #define CPU_ARCH_ARMv4		2
@@ -12,12 +14,56 @@
 #define CPU_ARCH_ARMv6		8
 #define CPU_ARCH_ARMv7		9
 
+#define CPU_IS_ARM920		0x41009200
+#define CPU_IS_ARM920_MASK	0xff00fff0
+
+#define CPU_IS_ARM926		0x41069260
+#define CPU_IS_ARM926_MASK	0xff0ffff0
+
+#define CPU_IS_ARM1176		0x410fb767
+#define CPU_IS_ARM1176_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A8	0x410fc080
+#define CPU_IS_CORTEX_A8_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A5	0x410fc050
+#define CPU_IS_CORTEX_A5_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A9	0x410fc090
+#define CPU_IS_CORTEX_A9_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A7	0x410fc070
+#define CPU_IS_CORTEX_A7_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A15	0x410fc0f0
+#define CPU_IS_CORTEX_A15_MASK	0xff0ffff0
+
+#define CPU_IS_PXA250		0x69052100
+#define CPU_IS_PXA250_MASK	0xfffff7f0
+
+#define CPU_IS_PXA255		0x69052d00
+#define CPU_IS_PXA255_MASK	0xfffffff0
+
+#define CPU_IS_PXA270		0x69054110
+#define CPU_IS_PXA270_MASK	0xfffff7f0
+
+#define cpu_is_arm(core) ((read_cpuid_id() & CPU_IS_##core##_MASK) == CPU_IS_##core)
+
 #ifdef CONFIG_CPU_32v4T
 #ifdef ARM_ARCH
 #define ARM_MULTIARCH
 #else
 #define ARM_ARCH CPU_ARCH_ARMv4T
 #endif
+#define cpu_is_arm920()	cpu_is_arm(ARM920)
+#define cpu_is_pxa250() cpu_is_arm(PXA250)
+#define cpu_is_pxa255() cpu_is_arm(PXA255)
+#define cpu_is_pxa270() cpu_is_arm(PXA270)
+#else
+#define cpu_is_arm920() (0)
+#define cpu_is_pxa250() (0)
+#define cpu_is_pxa255() (0)
+#define cpu_is_pxa270() (0)
 #endif
 
 #ifdef CONFIG_CPU_32v5
@@ -26,6 +72,9 @@
 #else
 #define ARM_ARCH CPU_ARCH_ARMv5
 #endif
+#define cpu_is_arm926() cpu_is_arm(ARM926)
+#else
+#define cpu_is_arm926() (0)
 #endif
 
 #ifdef CONFIG_CPU_32v6
@@ -34,6 +83,9 @@
 #else
 #define ARM_ARCH CPU_ARCH_ARMv6
 #endif
+#define cpu_is_arm1176()	cpu_is_arm(ARM1176)
+#else
+#define cpu_is_arm1176()	(0)
 #endif
 
 #ifdef CONFIG_CPU_32v7
@@ -42,6 +94,17 @@
 #else
 #define ARM_ARCH CPU_ARCH_ARMv7
 #endif
+#define cpu_is_cortex_a8() cpu_is_arm(CORTEX_A8)
+#define cpu_is_cortex_a5() cpu_is_arm(CORTEX_A5)
+#define cpu_is_cortex_a9() cpu_is_arm(CORTEX_A9)
+#define cpu_is_cortex_a7() cpu_is_arm(CORTEX_A7)
+#define cpu_is_cortex_a15() cpu_is_arm(CORTEX_A15)
+#else
+#define cpu_is_cortex_a8() (0)
+#define cpu_is_cortex_a5() (0)
+#define cpu_is_cortex_a9() (0)
+#define cpu_is_cortex_a7() (0)
+#define cpu_is_cortex_a15() (0)
 #endif
 
 #ifndef __ASSEMBLY__