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authorSascha Hauer <s.hauer@pengutronix.de>2019-07-12 07:10:19 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-07-12 07:10:19 +0200
commitf9dfe479ebacbb3efacef4525682546713b11597 (patch)
tree64b26ae51c86b9b1419d8a62baf5d2f5948f3f51 /arch/arm/include
parentac5e1f63aafb73a6ea2356822029ef391b6234d2 (diff)
parent9f30aa3f143eda22ba3cf9e36c05213239a2fe83 (diff)
downloadbarebox-f9dfe479ebacbb3efacef4525682546713b11597.tar.gz
barebox-f9dfe479ebacbb3efacef4525682546713b11597.tar.xz
Merge branch 'for-next/stm32'
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/gic.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index bd3a80cdf7..f83f528141 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -107,4 +107,33 @@
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
#define ICC_ASGI1R_EL1 S3_0_C12_C11_6
+#ifndef __ASSEMBLY__
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK 0xFFFF8000
+
+static inline unsigned long get_cbar(void)
+{
+ unsigned periphbase;
+
+ /* get the GIC base address from the CBAR register */
+ asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
+
+ /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+ * encode this). Bail out here since we cannot access this without
+ * enabling paging.
+ */
+ if ((periphbase & 0xff) != 0) {
+ pr_err("PERIPHBASE is above 4 GB, no access.\n");
+ return -1;
+ }
+
+ return periphbase & CBAR_MASK;
+}
+
+static inline unsigned long get_gicd_base_address(void)
+{
+ return get_cbar() + GIC_DIST_OFFSET;
+}
+#endif
+
#endif /* __GIC_H__ */