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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2020-07-01 11:11:17 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-11 06:15:44 +0200 |
| commit | 3c7606dde3793b7f13c82924caa85ad24423f91f (patch) | |
| tree | 7f06bead21c0c5c422d57756507ccab665a83254 /arch/arm/mach-at91 | |
| parent | 01474752795536d9dad1a7631f0f54c6c0191892 (diff) | |
| download | barebox-3c7606dde3793b7f13c82924caa85ad24423f91f.tar.gz barebox-3c7606dde3793b7f13c82924caa85ad24423f91f.tar.xz | |
ARM: at91: sama5d27-som1: add additional first stage entry point
The BootROM constrains us to a 64K big first stage bootloader. Add a PBL
entry point for a xload barebox that sets up the minimum necessary to
load a FAT32 barebox.bin from the SD-Card.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-at91')
| -rw-r--r-- | arch/arm/mach-at91/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/barebox-arm.h | 21 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h | 39 |
3 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 25ef854bf0..f388d00b8f 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -603,6 +603,7 @@ config MACH_SAMA5D27_SOM1 bool "Microchip SAMA5D27 SoM-1 Evaluation Kit" select SOC_SAMA5D2 select OFDEVICE + select MCI_ATMEL_SDHCI_PBL select COMMON_CLK_OF_PROVIDER help Select this if you are using Microchip's sama5d27 SoM evaluation kit diff --git a/arch/arm/mach-at91/include/mach/barebox-arm.h b/arch/arm/mach-at91/include/mach/barebox-arm.h new file mode 100644 index 0000000000..4a65c6f8fa --- /dev/null +++ b/arch/arm/mach-at91/include/mach/barebox-arm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AT91_BAREBOX_ARM_H_ +#define AT91_BAREBOX_ARM_H_ + +#include <asm/barebox-arm.h> + +#define SAMA5_ENTRY_FUNCTION(name, r4) \ + void name (u32 r0, u32 r1, u32 r2, u32 r3); \ + \ + static void __##name(u32); \ + \ + void NAKED __section(.text_head_entry_##name) name \ + (u32 r0, u32 r1, u32 r2, u32 r3) \ + { \ + register u32 r4 asm("r4"); \ + __barebox_arm_head(); \ + __##name(r4); \ + } \ + static void NAKED noinline __##name \ + (u32 r4) +#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h new file mode 100644 index 0000000000..35c92c43fc --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2-sip-ddramc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-1-Clause + * + * Copyright (C) 2014, Atmel Corporation + * + * SAMA5D27 System-in-Package DDRAMC configuration + */ + +#include <mach/at91_ddrsdrc.h> +#include <mach/ddramc.h> +#include <mach/sama5d2_ll.h> + +static inline void sama5d2_d1g_ddrconf(void) /* DDR2 1Gbit SDRAM */ +{ + struct at91_ddramc_register conf = { + .mdr = AT91_DDRC2_DBW_16_BITS | AT91_DDRC2_MD_DDR2_SDRAM, + + .cr = AT91_DDRC2_NC_DDR10_SDR9 | AT91_DDRC2_NR_13 | + AT91_DDRC2_CAS_3 | AT91_DDRC2_DISABLE_RESET_DLL | + AT91_DDRC2_WEAK_STRENGTH_RZQ7 | AT91_DDRC2_ENABLE_DLL | + AT91_DDRC2_NB_BANKS_8 | AT91_DDRC2_NDQS_ENABLED | + AT91_DDRC2_DECOD_INTERLEAVED | AT91_DDRC2_UNAL_SUPPORTED, + + .rtr = 0x511, + + .t0pr = AT91_DDRC2_TRAS_(7) | AT91_DDRC2_TRCD_(3) | + AT91_DDRC2_TWR_(3) | AT91_DDRC2_TRC_(9) | + AT91_DDRC2_TRP_(3) | AT91_DDRC2_TRRD_(2) | + AT91_DDRC2_TWTR_(2) | AT91_DDRC2_TMRD_(2), + + .t1pr = AT91_DDRC2_TRFC_(22) | AT91_DDRC2_TXSNR_(23) | + AT91_DDRC2_TXSRD_(200) | AT91_DDRC2_TXP_(2), + + .t2pr = AT91_DDRC2_TXARD_(2) | AT91_DDRC2_TXARDS_(8) | + AT91_DDRC2_TRPA_(4) | AT91_DDRC2_TRTP_(2) | + AT91_DDRC2_TFAW_(8), + }; + + sama5d2_ddr2_init(&conf); +} |