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| author | Alexander Shiyan <shc_work@mail.ru> | 2013-03-11 13:26:32 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-03-11 22:17:42 +0100 |
| commit | 57ec3a893195bae0bc40b2b2d56d95b6a397468a (patch) | |
| tree | b0c76e52e938adee2f90f9c6cbaea12fe6671212 /arch/arm/mach-clps711x | |
| parent | 5f106e7b22e123b85b437fd61ceabb774bf5bde8 (diff) | |
| download | barebox-57ec3a893195bae0bc40b2b2d56d95b6a397468a.tar.gz barebox-57ec3a893195bae0bc40b2b2d56d95b6a397468a.tar.xz | |
ARM: clps711x: Fix setup bus wait state scaling factor for 13Mhz mode
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-clps711x')
| -rw-r--r-- | arch/arm/mach-clps711x/lowlevel.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c index 193f61aa6e..58306f29fc 100644 --- a/arch/arm/mach-clps711x/lowlevel.c +++ b/arch/arm/mach-clps711x/lowlevel.c @@ -21,12 +21,12 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult) { u32 cpu, bus; - /* Setup base clocking, Enable SDQM pins */ - writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); - asm("nop"); - /* Check if we running from external 13 MHz clock */ if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) { + /* Setup bus wait state scaling factor to 2 */ + writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); + asm("nop"); + /* Check valid multiplier, default to 74 MHz */ if ((pllmult < 20) || (pllmult > 50)) pllmult = 40; @@ -42,11 +42,15 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult) cpu = pllmult * 3686400; if (cpu >= 36864000) - bus = cpu /2; + bus = cpu / 2; else bus = 36864000 / 2; - } else + } else { bus = 13000000; + /* Setup bus wait state scaling factor to 1 */ + writel(0, SYSCON3); + asm("nop"); + } /* CLKEN select, SDRAM width=32 */ writel(SYSCON2_CLKENSL, SYSCON2); |