ARM: clps711x: Move basic lowlevel initialization in common CLPS711X location

One lowlevel initialization will be used on any CLPS711X-target,
so move it in the common location.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 70 insertions, 1 deletions

diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 41012bc016..69a4a3c47c 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -1 +1,2 @@
-obj-y += clock.o devices.o reset.o
+obj-y += clock.o devices.o lowlevel.o reset.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 048992a361..5b8fe829c0 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -281,4 +281,6 @@
 #define MEMCFG_WAITSTATE_2_0	(14 << 2)
 #define MEMCFG_WAITSTATE_1_0	(15 << 2)
 
+void clps711x_barebox_entry(void);
+
 #endif
diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c
new file mode 100644
index 0000000000..cd3216a68a
--- /dev/null
+++ b/arch/arm/mach-clps711x/lowlevel.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <sizes.h>
+
+#include <asm/io.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#include <mach/clps711x.h>
+
+void __naked __bare_init clps711x_barebox_entry(void)
+{
+	const u32 pllmult = 50;
+	u32 cpu, bus;
+
+	/* Setup base clocking, Enable SDQM pins  */
+	writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3);
+	asm("nop");
+
+	/* Check if we running from external 13 MHz clock */
+	if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) {
+		/* Setup PLL */
+		writel(pllmult << 24, PLLW);
+		asm("nop");
+
+		/* Check for old CPUs without PLL */
+		if ((readl(PLLR) >> 24) != pllmult)
+			cpu = 73728000;
+		else
+			cpu = pllmult * 3686400;
+
+		if (cpu >= 36864000)
+			bus = cpu /2;
+		else
+			bus = 36864000 / 2;
+	} else
+		bus = 13000000;
+
+	/* CLKEN select, SDRAM width=32 */
+	writel(SYSCON2_CLKENSL, SYSCON2);
+
+	/* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */
+	writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 |
+	       SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF);
+
+	/* Setup Refresh Rate (64ms 8K Blocks) */
+	writel((64 * bus) / (8192 * 1000), SDRFPR);
+
+	/* Disable UART, IrDa, LCD */
+	writel(0, SYSCON1);
+	/* Disable PWM */
+	writew(0, PMPCON);
+	/* Disable LED flasher */
+	writew(0, LEDFLSH);
+
+	barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0);
+}