arm: add highbank support

currently only tested under qemu

qemu-system-arm -M highbank -nographic -m 4089 -kernel build/highbank/arch/arm/pbl/zbarebox -tftp "." -drive id=disk,if=ide,file=disk.img -device ide-drive,drive=disk,bus=ide.0

with:
 - timer (AMBA SP804)
 - uart (AMBA PL011)
 - gpio (AMBA PL061)
 - ahci
 - net (XGMAC)

Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

10 files changed, 266 insertions, 0 deletions

diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
new file mode 100644
index 0000000000..47c6405eb1
--- /dev/null
+++ b/arch/arm/mach-highbank/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_HIGHBANK
+
+config ARCH_TEXT_BASE
+	hex
+	default 0x03f00000
+
+config BOARDINFO
+	default "Calxeda Highbank" if MACH_HIGHBANK
+
+choice
+	prompt "Calxeda Board type"
+
+config MACH_HIGHBANK
+	bool "Calxeda Highbank"
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
new file mode 100644
index 0000000000..3f01cbb01c
--- /dev/null
+++ b/arch/arm/mach-highbank/Makefile
@@ -0,0 +1,3 @@
+obj-y += core.o
+obj-y += devices.o
+obj-y += reset.o
diff --git a/arch/arm/mach-highbank/core.c b/arch/arm/mach-highbank/core.c
new file mode 100644
index 0000000000..3423c55b21
--- /dev/null
+++ b/arch/arm/mach-highbank/core.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware/arm_timer.h>
+
+#include <mach/devices.h>
+
+#include "sysregs.h"
+
+void __iomem *sregs_base = IOMEM(0xfff3c00);
+
+
+static void highbank_clk_init(void)
+{
+	struct clk *clk;
+
+	clk = clk_fixed("dummy_apb_pclk", 0);
+	clk_register_clkdev(clk, "apb_pclk", NULL);
+
+	clk = clk_fixed("pclk", 150000000);
+	clk_register_clkdev(clk, NULL, "sp804");
+	clk_register_clkdev(clk, NULL, "uart-pl011");
+}
+
+static void highbank_sp804_init(void)
+{
+	amba_apb_device_add(NULL, "sp804", DEVICE_ID_SINGLE, 0xfff34000, 4096, NULL, 0);
+}
+
+static int highbank_init(void)
+{
+	highbank_clk_init();
+	highbank_sp804_init();
+
+	return 0;
+}
+postcore_initcall(highbank_init);
diff --git a/arch/arm/mach-highbank/devices.c b/arch/arm/mach-highbank/devices.c
new file mode 100644
index 0000000000..6d75864306
--- /dev/null
+++ b/arch/arm/mach-highbank/devices.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#include <common.h>
+#include <sizes.h>
+
+#include <linux/amba/bus.h>
+
+#include <asm/memory.h>
+
+#include <mach/devices.h>
+
+void highbank_add_ddram(u32 size)
+{
+	arm_add_mem_device("ram1", 0x00000000, size);
+	add_mem_device("nvram", 0xfff88000, SZ_32K, IORESOURCE_MEM_WRITEABLE);
+}
+
+void highbank_register_uart(void)
+{
+	amba_apb_device_add(NULL, "uart-pl011", DEVICE_ID_SINGLE, 0xfff36000, 4096, NULL, 0);
+}
+
+void highbank_register_ahci(void)
+{
+	add_generic_device("ahci", DEVICE_ID_SINGLE, NULL, 0xffe08000,
+			0x10000, IORESOURCE_MEM, NULL);
+}
+
+void highbank_register_xgmac(unsigned id)
+{
+	resource_size_t start;
+
+	switch (id) {
+	case 0:
+		start = 0xfff50000;
+		break;
+	case 1:
+		start = 0xfff51000;
+		break;
+	default:
+		return;
+	}
+
+	add_generic_device("hb-xgmac", id, NULL, start, 0x1000,
+				IORESOURCE_MEM, NULL);
+}
+
+void highbank_register_gpio(unsigned id)
+{
+	resource_size_t start;
+
+	switch (id) {
+	case 0:
+		start = 0xfff30000;
+		break;
+	case 1:
+		start = 0xfff31000;
+		break;
+	case 2:
+		start = 0xfff32000;
+		break;
+	case 3:
+		start = 0xfff33000;
+		break;
+	default:
+		return;
+	}
+
+	amba_apb_device_add(NULL, "pl061_gpio", id, start, 0x1000, NULL, 0);
+}
diff --git a/arch/arm/mach-highbank/include/mach/clkdev.h b/arch/arm/mach-highbank/include/mach/clkdev.h
new file mode 100644
index 0000000000..04b37a8980
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/debug_ll.h b/arch/arm/mach-highbank/include/mach/debug_ll.h
new file mode 100644
index 0000000000..4cdbb3ce51
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/debug_ll.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Jean-Christophe PLAGNIOL-VILLARD <plagniol@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __MACH_DEBUG_LL_H__
+#define   __MACH_DEBUG_LL_H__
+
+#include <linux/amba/serial.h>
+#include <io.h>
+
+#define UART_BASE 0xfff36000
+
+static inline void PUTC_LL(char c)
+{
+	/* Wait until there is space in the FIFO */
+	while (readl(UART_BASE + UART01x_FR) & UART01x_FR_TXFF);
+
+	/* Send the character */
+	writel(c, UART_BASE + UART01x_DR);
+
+	/* Wait to make sure it hits the line, in case we die too soon. */
+	while (readl(UART_BASE + UART01x_FR) & UART01x_FR_TXFF);
+}
+#endif
diff --git a/arch/arm/mach-highbank/include/mach/devices.h b/arch/arm/mach-highbank/include/mach/devices.h
new file mode 100644
index 0000000000..2cf2b6161c
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/devices.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __ASM_ARCH_DEVICES_H__
+#define __ASM_ARCH_DEVICES_H__
+
+void highbank_add_ddram(u32 size);
+
+void highbank_register_uart(void);
+void highbank_register_ahci(void);
+void highbank_register_xgmac(unsigned id);
+void highbank_register_gpio(unsigned id);
+
+#endif /* __ASM_ARCH_DEVICES_H__ */
diff --git a/arch/arm/mach-highbank/include/mach/gpio.h b/arch/arm/mach-highbank/include/mach/gpio.h
new file mode 100644
index 0000000000..306ab4c9f2
--- /dev/null
+++ b/arch/arm/mach-highbank/include/mach/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-highbank/reset.c b/arch/arm/mach-highbank/reset.c
new file mode 100644
index 0000000000..eb1d11542d
--- /dev/null
+++ b/arch/arm/mach-highbank/reset.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#include <common.h>
+#include <io.h>
+
+#include <mach/devices.h>
+
+#include "sysregs.h"
+
+void __noreturn reset_cpu(ulong addr)
+{
+	hingbank_set_pwr_hard_reset();
+	asm("	wfi");
+
+	while(1);
+}
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
new file mode 100644
index 0000000000..c879422194
--- /dev/null
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+
+#include <io.h>
+
+extern void __iomem *sregs_base;
+
+#define HB_SREG_A9_PWR_REQ		0xf00
+#define HB_SREG_A9_BOOT_STAT		0xf04
+#define HB_SREG_A9_BOOT_DATA		0xf08
+
+#define HB_PWR_SUSPEND			0
+#define HB_PWR_SOFT_RESET		1
+#define HB_PWR_HARD_RESET		2
+#define HB_PWR_SHUTDOWN			3
+
+static inline void hingbank_set_pwr_suspend(void)
+{
+	writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+
+static inline void hingbank_set_pwr_shutdown(void)
+{
+	writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+
+static inline void hingbank_set_pwr_soft_reset(void)
+{
+	writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+
+static inline void hingbank_set_pwr_hard_reset(void)
+{
+	writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
+}
+
+#endif